FPGA-based Real-time Lightweight Image Edge Detection Acceleration Circuit Design

Since the edge of the image contains important information of the image,the edge of the image is where the grayscale changes drastically,and edge detection is an important part of image processing,which has a wide range of applications in industrial electronics,medical imaging and so on.With the increasing image resolution,the complexity of the image edge algorithm continues to increase,and in many application scenarios,stricter requirements are placed on the speed,hardware overhead,and power consumption of image edge detection.Due to the advantages of parallel processing,good programmability,and low power consumption,FPGA-based image processing technology has a good development prospect.This paper focuses on key technical issues such as how to improve the speed and real-time performance of image edge detection.The main research contents include:(1)Aiming at the problems of long storage time,slow operation speed,and inability to realize real-time processing of video image data processing traditionally using CPU as the carrier,a design based on FPGA hardware structure processing is proposed to improve the processing speed and real-time performance of the system.This research starts from the classical edge detection algorithm,based on the basic principle of edge detection algorithm,compares and analyzes the characteristics of the existing edge detection algorithm systematically,and points out that the use of Sobel algorithm on FPGA platform can realize real-time lightweight image edge detection.Design based on FPGA development board(AX516),the system consists of three parts:image acquisition module,image processing module,and image display module.The camera OV5640 is used for image acquisition,and the register configuration is performed through the I2 C interface to generate a picture with a pixel size of 1024×768 and RGB565 image format,and store it in DDR3.After grayscale conversion,edge detection is performed,and the detection result is displayed through the VGA interface.,to achieve the purpose of real-time detection,the entire process of detection and control is less than 30 ms.(2)When 5×5 two-dimensional convolution is performed on an image with a pixel of 1024×768,when the calculation is performed by calling the IP core,there are problems of large amount of calculation,high power consumption and large delay.The 8-bit multiplier replaces the multiplication IP core,and the addition part is realized by the compression structure of 4(input)-2(output)compression and 5(input)-2(output)compression,based on the 28 nm standard silicon-based CMOS process,The approximate multiplier has a delay of 0.25 ns,and the exact multiplier has a delay of 0.47 ns,an improvement of nearly 46%,and the power consumption is reduced from 1140 m W to 364 m W.Comparing the images produced by the two structures,the PSNR(peak signaltonoise ratio)is 60.47 d B and the SSIM(structural similarity)is 0.9942,and the image quality is almost undistorted.(3)The research results of the application of automatic gain control system based on FPGA are introduced.The circuit consists of five parts,which are VGA module,peak detection module,voltage comparison module,FPGA development board,and voltage selection circuit.Through the test of the automatic gain control circuit,the gain is adjustable at 20 d B,10 d B,0 d B,and-10 d B under different input electrical signals.The test results show that the settling time of the automatic gain circuit designed in this paper is 54 μs.Compared with the traditional automatic gain circuit settling time of 4.3 ms,the design of this paper reduces the system response speed by 2 orders of magnitude.