| With the continuous improvement of mobile communication rate and the wide application of software radio in radar and signal modulation,the role of digital signal processing module cannot be ignored more and more.Signal processing mainly includes two parts,digital up-sampling and down-sampling.Data transmission is getting faster and faster,and the traditional serial transmission structure is no longer suitable for the current transmission needs.At the same time,private network communication occupies a dominant position in the communication industry.For different enterprise customers,following strict frequency transmission,integer multiple sampling rate conversion has been difficult to support the increasing frequency band requirements.In order to solve the above problems,this thesis mainly studies the digital signal processing in the high-speed transmission environment(the sampling rate is GHz level),combines the parallel decomposition algorithm,the fine decimal interpolation algorithm,etc.Finally,a 4-channel fully parallel sampling rate conversion system that can realize digital resampling is designed.The proposed system has a higher operating frequency than traditional ones,a large convertible multiple,and can realize any multiple sampling rate conversion operation.The main research content of this thesis is as follows:1.Design of up-sampling system.Firstly,the impulse response and amplitudefrequency characteristics of various interpolation functions were compared,and Lagrange interpolation was selected after observing the degree of fitting to the ideal function,the influence of high-order(7th-order)interpolation on the interpolation effect was deduced by using the Lagrange algorithm,the filter structure adopts the Farrow structure suitable for polynomial interpolation.The design of the 4-channel all-parallel up-sampling system includes three modules: parallelization of filter banks,data cache,control and multiply-accumulate unit.Parallel decomposition of the filter bank by comparing the fast FIR algorithm and the fast convolution algorithm,it is found that the number of filter taps in the implementation structure of the fast convolution algorithm is small.Moreover,after processing by the two algorithms,it is consistent with the theoretical waveform under the serial structure,and the parallel decomposition is correct.The data cache module adopts the FIFO structure of double-ended RAM.What is inconsistent with the tradition is that the address of the output data is not selfincrementing,but changes according to the change of the interpolation reference point.The control and multiply-add unit module is responsible for outputting the address control word and interpolation interval of the FIFO structure.In order to improve the operation speed and ensure the accuracy of the operation,the multiply-add unit adopts pipeline technology to convert the multiplication into shift addition and calculates the number of digits of the output result.The truncation process saves resources under the premise of ensuring accuracy.The final test system output error is about 1%,and the design is successful.2.Design of down-sampling system.The spectral aliasing phenomenon that will be generated in the extraction process is analyzed.The filter structure adopts a half-band filter,which has the advantages of symmetrical parameters and half of them being 0,greatly reducing the computational complexity.The design of the 4-channel all-parallel down-sampling system includes three modules: anti-aliasing filter,decimator,and interpolator.Use the software simulation platform to adjust the parameters,balance the relationship between the order and the transition band of the passband,and design a low-pass anti-aliasing filter.The extractor is integer multiple extraction,in order to achieve any multiple,a fine decimal multiple interpolator is connected after the extraction to realize down-sampling processing of any multiple.The output result needs to be truncated,and the error is within 0.5%.The design is successful. |
PDF Full Text Request