The Research On Wideband Radar Signal Acquisition And Processing Technology

Broadband radar signal acquisition and processing technology is an important research direction in the field of broadband imaging radar and electronic reconnaissance.In this paper,based on SRIO bus multi-board interconnection,a broadband radar signal acquisition and processing system is designed to realize the functions of wideband radar signal acquisition,pre-processing,real-time imaging and electronic reconnaissance.The main contributions of this dissertation can be summarized as follows:1)The research status of the broadband radar signal acquisition and processing at home and abroad are analyzed and summarized,and then a technical scheme is proposed to meet the project requirements.The theory and technology of broadband radar signal acquisition and processing is analyzed.Finally,an acquisition and processing program is proposed.This acquisition and processing system includes high-speed data acquisition module and real-time signal processing module.The two module is connected by the SRIO new high-speed bus interconnection.2)According to the task demand,the hardware design of high-speed acquisition module is analyzed.The EV10AQ190 A chip is used as the sampling core and the VC6VLX240 T chip is the main controller.By using FPGA internal high-level logic resources ISERDES1 and IODELAY1,combined with regional clock resources,a high-speed source synchronous sampling signal serial-parallel conversion logic is designed.The data output order of EV10AQ190 A in different working modes is analyzed and the corresponding data sequence is adjusted.At last,the test results of 1: 4 serial-to-parallel conversion and data sequence adjustment in single channel mode are given.3)According to the requirements of real-time processing tasks,the core architecture and the main chips are analyzed and selected based on micro,general purpose,high performance and low power consumption.The card is mainly composed by a VC6VLX240 T chip and two TMS320C6678 chip.By combination with the multi-output high-speed clock chip AD9516-3 and the single-chip CY7C68053,an unified output clock is designed.Based on the digital switching power supply UCD9244 + UCD7242,the DSP core voltage can be adjusted in real-time.Then the power consumption of the DSP is reduced.The high-speed large-capacity data cache is realized by DDR3 SDRAM.High-speed serial bus SRIO is used to realize the interconnection and expansion between the chips and the boards.