Data Acquisition And TCP/IP Compact Protocol Stack Implementation On FPGA

Data acquisition and Ethernet transmission systems are widely used in aerospace,industrial intelligence and many other industries,and today’s application scenarios are becoming increasingly complex,and the requirements for diversified and refined collection data,highspeed and real-time feedback transmission are constantly increasing.Traditional MCU-ADC data acquisition systems are difficult to meet specific acquisition needs,and traditional W5300 hardware TOE chips are difficult to achieve streamlined and efficient Ethernet transmission in the environment of high-speed data acquisition.Consequently,the research and design of a versatile and flexible high-performance data acquisition and Ethernet transmission system is an important topic that needs to be continuously overcome and improved in today’s society.This design aims to realize high-precision multiplex data acquisition and TCP/IP simplified hardware stack based on FPGA research,and provide an easily expandable,efficient and stable Ethernet hardware stack transmission feasibility scheme for data acquisition in high-speed environment.The key research contents of this paper are as follows:1)Taking wind tunnel free-flight multiple-channel signal sensing as the application scenario,the overall framework of data acquisition and TCP/IP simplified protocol stack transmission system is designed.Combined with the sampling theorem,determine the system sampling rate and the matching serial transmission interface;This paper studies the application environment and Ethernet multilayer architecture,gives the tailoring scheme of the TCP/IP lite protocol stack.Build the system hardware platform,analyze the performance advantages of the Xilinx-XC7K325 T main control chip,and build the PHY chip communication interface based on the RGMII interface transmission mode2)FPGA sequential logic design for data acquisition,design the logical architecture of multi-channel data acquisition combined with four-wire SPI protocol,and complete the logical design of data acquisition state machine,driving clock and data processing module.3)FPGA logic design of TCP/IP compact protocol stack,combined with TCP/IP five-layer network architecture,the Ethernet frame transmission and reception of the data link layer and the CRC-32 checksum algorithm logic design at the end of the frame.Network layer IP protocol,ARP protocol and ICMP protocol development and design,transport layer UDP transmission and FPGA design of basic functions of TCP.4)Test and verify the system,simulate SPI communication of the data acquisition module,write a simulation incentive source to simulate the communication mechanism between the two sides of the protocol stack,and perform functional simulation of the TCP/IP compact protocol stack subprotocol;On the basis of completing the physical verification of the submodule protocol,the joint physical test of system level data acquisition and Ethernet transmission is carried out.Eventually,the simulation verification and performance test of the system are carried out,and the data acquisition accuracy of the system reaches ±0.07%,the transmission bandwidth of the TCP/IP compact protocol stack reaches 333 Mbps,and the average round-trip time RTT is 660 us.The system is not only suitable for specific free-flight on-board environments,but also easy to expand and versatile.