Research And FPGA Implementation Of TCP/IP Hardware Protocol Stack In Data Acquisition System

Data acquisition system is widely used in many fields,such as industrial control.With more and more precise,intelligent,multi-channel acquisition equipment and scenarios to be tested,the ability of acquisition and transmission system is put forward higher and higher requirements.The traditional shelf data acquisition system is difficult to meet the specific needs,but the non-standard product acquisition system has a strong pertinence,and the price is expensive,the structure is complex,it is difficult to apply to the general acquisition application scenarios.Therefore,to realize a data acquisition system with high performance,high flexibility and low cost is the urgent need of the current social and industrial development.With the rapid development of integrated circuit and information science and technology,new ideas are provided for the high-performance and integrated design of data acquisition system.With the help of the idea of network offload engine,the logic design of TCP/IP stack is realized based on FPGA,and an Ethernet transmission link with high transmission rate,high reliability,flexibility and low cost is realized.The purpose of this paper is to study the implementation scheme of hardware design of software protocol based on hardware programmable devices,and to provide a feasible scheme for high-speed data unloading and transmission link acceleration in the field of distributed data acquisition.Firstly,combining the functions and characteristics of data acquisition system and TCP/IP,this paper proposes a cutting scheme of TCP/IP family,which only retains the necessary protocol to ensure high-speed data transmission and reliability.The basic function of Ethernet TCP/IP communication is realized by adopting the design method of layered processing and modularization according to the order of "receiving analysis-data processing-group frame sending".On this basis,in-depth study of the key technologies of TCP,using standard algorithms in FPGA to achieve timeout and retransmission;design TCP sending window based on RAM;improve congestion control algorithm based on congestion window packet count,so that it has higher regulation efficiency in the process of hardware logic processing and batch data highspeed transmission.In addition,the request and reply queue management mechanism,the check and pre-calculation algorithm and the CRC32 pre-calculation algorithm are proposed,to improve the unloading and encapsulation rate of network data.Secondly,based on the real Ethernet communication data,the test benches are written,and a comprehensive simulation is established.The design details and function realization of TCP/IP stack are analyzed in detail based on the simulation waveform to ensure the logical correctness of the design and provide a large number of examples for the actual test and application.Finally,the Gigabit Ethernet physical platform is built.The test results show that the ARP response,ICMP echo response,UDP data receiving and sending,connection establishment,data communication,connection termination,timeout retransmission and recovery functions of TCP/IP hardware stack are all implemented correctly.According to the test of TCP high-speed transmission performance,the results show that 63% of the network utilization rate can be achieved in the general Ethernet channel with the capacity of gigabytes,and 300 Mbit/s rate can be achieved in the stable stage of TCP transmission,with stable performance.Compared with the traditional and ASIC based implementation,this design has a good advantage in transmission processing speed,flexibility,universality and cost.It is suitable for a wide range of data acquisition and transmission systems and has good practical application value.