Design Of Low Jitter Phase Locked Loop For Wireless Communication

With the rapid development of wireless communication technology,Wi Fi,Bluetooth and other short-range wireless communication technologies play an increasingly prominent role in the mobile terminal scene.With the upgrading of communication standards,more stringent requirements are put forward for the performance of RF transceiver.Phase locked loop(PLL)provides local oscillator signal for transceiver,which seriously affects the quality of transmitting and receiving signal.Therefore,the research on low jitter clock generation circuit is of great significance.For wireless communication applications,a Charge Pump Phase Locked Loop(CP-PLL)is designed to meet the jitter requirements of local oscillator signal in RF transceiver system.Starting from the structure principle and noise characteristics of CP PLL,this thesis analyzes the noise of each module and the characteristics of noise transfer function in detail.The innovation of this thesis mainly focuses on the structural improvement of traditional charge pump and voltage controlled oscillator(VCO)to improve the linearity of charge pump and reduce the phase noise of VCO.The offset current is introduced to suppress noise folding of the Sigma Delta Modulator due to the nonlinear of Charge Pump.Aiming at the problem that flicker noise of the tail current of LC VCO and the noise at the second harmonic frequency mixing to the fundamental frequency will worse the phase noise,the second harmonic filter network and tail resistance structure are applied to effectively reduce the noise level of VCO.The output of the oscillator realizes the requirements of the system for the quadrature signal by adding AC buffer and quadrature frequency divider.To further reduce the phase noise introduced by the reference clock,the crystal oscillator is integrated in this design,the three-point structure of Pierce oscillator is adopted,and the duty cycle detection and peak detection circuit is set to adjust the duty cycle of output waveform and starting speed of the crystal oscillator.Each module of the whole PLL circuit uses a separate low dropout regulator(LDO)as supply to avoid spurious caused by power ripple and deterioration of noise performance.Based on TSMC 28nm CMOS process,this thesis uses Spectre,AMS and EMX tools to carry out pre-simulation,layout drawing and post simulation verification of each module and the whole system.Finally,the chip flow and test verification are completed.The chip test results show that the overall function of PLL is normal.The operating frequency range of PLL is 2.42GHz-3.27GHz.The phase noise measured at the center frequency of 3.27GHz at 1MHz frequency offset is-122dbc/Hz,RMS jitter is 285.945fs,chip area is 0.78mm~2,and the core current consumption of PLL is 67.2m A.From the test results,the performance of PLL can meet the design index and requirements of actual RF transceiver for LO signal.