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Trusted Chip Soft Core Design Based On RISC-V Architecture

Posted on:2024-09-14Degree:MasterType:Thesis
Country:ChinaCandidate:X ZhangFull Text:PDF
GTID:2568307058951599Subject:Master of Electronic Information (Professional Degree)
Abstract/Summary:
In response to the information security needs of China’s industrial control field,traditional security mechanisms are difficult to effectively respond to logical flaws attacks,and security protection measures lack proactive control on the terminal.To defend against external threats,the concept of active defense is proposed in Trusted Computing 3.0,and a trusted chip,as the trusted computing node of the active immune defense system,is a key component to achieve trusted protection functions.It can rely on national cryptographic algorithms in the trusted cryptographic module to provide functions such as integrity measurement and information encryption and decryption for external devices.In order to realize the trusted active logic control function of the trusted chip,a microprocessor is used as the computing control unit.Within the existing processor architecture,the RISC-V architecture has a rich and open-source ecosystem with modular instruction sets,allowing users to choose different modules according to their needs.Therefore,developing a trusted chip based on the RISC-V architecture processor using FPGA has significant value and meaning.A self-designed 32-bit RISC-V soft core processor is used as the trusted control unit of the trusted chip,supporting the RV32 I instruction set and using a six-stage pipeline to solve pipeline hazards.Using AXI as the bus system and IP cores to implement UART,SPI,GPIO,and other peripherals,SM-3,SM-4 national cryptographic algorithms,and a true random number generator are implemented in the trusted cryptographic module in hardware,improving the security and computing speed of encryption and decryption,while SM-2 asymmetric cryptographic algorithm is implemented in software.The trusted chip board is tested and validated,and the processor core is functionally simulated,showing normal operation at each pipeline stage.Running the Coremark/MHz test program at a clock frequency of 50 MHz,its performance is better than that of similar designs.The processor soft core is burned into Xilinx XC7A200 T FPGA through EDA tools for prototype verification.The trusted chip board is connected to the domestic Feiteng D2000 motherboard through PCIe interface,and the driver file is compiled and loaded in the desktop operating system environment of Kylin Linux.A demo program is compiled and written to verify the functions of SM-3,SM-4,and SM-2 encryption and decryption,achieving encryption and decryption operations on data.The overall results show that the trusted chip board can establish communication connection with the host and perform encryption and decryption of data,achieving integrity measurement of the host.
Keywords/Search Tags:RISC-V, Trusted computing, Cryptographic algorithm, Soft processor, Pipeline
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