Design And Implementation Of Specific Cryptographic Instructions Based On RISC-V Architecture

With the rapid development of 5G communication and Internet of Things technology,large amounts of critical data generated by edge devices are transferred through the network to more powerful computing terminals.Traditional cryptographic technology deployment schemes cannot be well deployed on terminal devices due to the limited computing resources and limited storage space.The RISC-V instruction set is a better choice for domain specific architecture because of its compact architecture and modular design philosophy.By adding cryptographic arithmetic unit to the general purpose processor based on RISC-V architecture,the processor can obtain high cryptographic arithmetic performance while not losing the ablity of general purpose computation.The main work and innovation points of this paper are as follows:Based on the analysis of the characteristics of different instruction subsets of RISC-V architecture,a symmetric cipher oriented instruction format is proposed.In this paper,the architecture of instruction decoding,fetching and executing circuit of RISC-V processor is studied deeply,and a design scheme of multi-read and write instruction circuit supporting cipher operation instruction format is proposed,which solves the problems of resource conflict and data conflict arising from it.The characteristics of permutation operation in symmetric cryptography are analyzed,and instructions of joint shifting operation and permutation operation for symmetric cryptography are proposed,which can support shifting operation with different bit widths and different directions.A new Reconfigurable Joint Shifter Module(RJSM)based on CMOS transport Gate,NMOS single-tube transport Gate and standard cell library is designed.Experiments show that compared with S-RJSM based on standard digital unit library,the delay of CMOS gate based joint shift circuit(C-RJSM)and NMOS single-tube gate based joint shift circuit(N-RJSM)is reduced by 85.30% and 50.69%,respectively.The power-delay product is reduced by 97.27%and 90.43%,respectively.The arithmetic operation characteristic of symmetric cipher is analyzed,and the modular operation instruction and finite field operation instruction oriented symmetric cipher are presented.Therefore,we design a Reconfigurable Modulo Arithmetic Unit(RMAU)by eliminating some high product positions,expanding the Wallace tree compression and summative process,and reducing critical path,which supports 5 modulo multiplication operations,3 modulo addition operations and three accumulation operations.The experimental results show that RMAU reduces the computation delay by 39%,44% and 47%,respectively,while having high functional coverage compared with other modular computing units.This paper analyzes the requirements of table lookup operation in cryptographic operation,makes full use of data storage resources,and puts forward the S-box table lookup address generation scheme without modifying the original implementation architecture.The 8-8 and 4-4 table lookup operation instructions are designed,so that one instruction can complete table lookup operation for 4 or 8 times,effectively improving the efficiency of table lookup.The software and hardware verification environment based on FPGA platform is established,and the resource occupancy of cryptographic operation unit is evaluated.The results show that the hardware resource required by the dedicated cryptographic instruction operation unit accounts for about 21% of the cryptographic processor.Three cryptographic algorithms,SM4,AES and ZUC,are implemented by special cryptographic instruction programming,and compared with the performance of general processors,the research shows that the number of instructions required by special cryptographic instruction programming to achieve SM4,AES and ZUC is reduced by 62.41%,77.35% and 49.23%,respectively.The number of cycles required decreased by 60.70%,82.61% and 48.54%,respectively.