Design And Implementation Of FPGA-Based High-Performance Data Converter Test System

Analog-to-digital converters(ADC)and digital-to-analog converters(DAC)are indispensable bridges between the digital and analog worlds.With the rapid development of mobile Internet of Things,5G,bio-electronic medical,autonomous driving and other fields,high-speed and high-precision ADC/DACs are emerging in large numbers.The existing large automatic test equipment(ATE)has shortcomings such as system complexity,difficult operation,high cost,and lack of flexibility when testing ADC/DAC,so it is urgent to update and optimize to keep pace with the times.To address these problems,this study aims to design,implement and verify a high-performance,high-efficiency and low-cost ADC/DAC test system,and provide technical support for high-speed and high-precision ADC/DAC performance parameter testing.The following work is specifically carried out:(1)This paper deeply investigates the basic principles,performance parameters and existing test methods of ADC/DAC,and optimizes the parametric test method of ADC/DAC.For the spectral leakage problem of ADC under non-coherent sampling conditions,a combined four-parameter sine curve fitting algorithm is proposed.The result of the three-parameter fitting is used as the initial value of the four-parameter fitting to obtain the real test signal,and then the corresponding coherent sine wave is calculated and replaced according to this test signal to reconstruct the new test data,which realizes the accurate testing of ADC dynamic parameters.The algorithm requires no iteration and absolute convergence,which greatly reduces the test time.To address the problem that the existing DAC static parameter test takes too long,this paper connects a high-precision ADC at the DAC output to convert the DAC output results into digital signals for processing,and the whole test process is carried out at the digital side,avoiding tedious manual calibration and improving test efficiency.(2)A hardware platform with FPGA as the control core is designed.The platform has the following advantages compared with existing test platforms: 1)Multiple digital interfaces CMOS,LVDS and JESD204 B are reserved(clock frequency up to 12.5 GHz);2)DDR3SDRAM is used as the memory for sampling data during conversion,with data throughput rate up to 20 Gb/s,which meets the requirements of high bandwidth,high storage depth and high speed real-time data during high performance testing(3)EMMC is used to achieve high-speed mass storage,with a total storage capacity of 2 TB and 4 pieces of storage speed up to250 MB/s ×4(28)1 GB/s.Based on the method of software and hardware collaborative design and software layered architecture,the modular software design of the test system is carried out to realize the overall control of the test system by the main control computer.(3)Setting up the experimental environment based on the designed test system: three typical high-speed high-precision ADC chips and one typical high-speed high-precision DAC chip are used as test devices,and the system test is conducted from the static parameters and dynamic parameters of ADC/DAC chips,which effectively verifies the performance of the hardware platform and each tested sub-board.The test results verify the effectiveness and versatility of the test system,which meets the test requirements and has good application and promotion value.