Research And Optimization Of ADC Parameter Test Method On V93000 Platform

As an indispensable part of the digital age,analog-to-digital converter(ADC)is widely used in various fields such as digital communications,automobiles,and medical equipment.But whether it is an ADC module integrated on a SOC chip or an independent ADC chip,it is essential to test its performance before mass production.This article will use Advantest's V93000 test machine to test the performance of an ADC chip.In the dynamic parameter test process,the test accuracy has serious errors due to the influence of spectrum leakage.Therefore,reducing spectrum leakage and improving test accuracy is one of the research contents of this article.With the popularity of automated testing in the field of integrated circuit testing,using ATE testing machines to complete chip testing has become the first choice of many IC design companies.Since the pre-design of ADC chips requires high cost,it is necessary to control the test time in the chip test link to reduce the production cost of the chip,in addition,it is also necessary to ensure that the test accuracy is not affected.Therefore,another research content of this article is to optimize the test program to reduce the test time when the accuracy meets the requirements.Firstly,this article introduces the significance of the research and current research status of the subject.Secondly,the principle and method of ADC parameter test under V93000 are explained and the chip under test is briefly analyzed.Then introduce the V93000 test hardware and Smar Test test software,complete the hardware parameter configuration and test environment construction according to the chip manual.Finally,further research is carried out on the accuracy optimization and test time optimization in the dynamic parameter test process.In terms of testing accuracy optimization,firstly,the method of adding a window function to sampling can solve the problem of discontinuity of the waveform signal caused by incoherent sampling and reduce spectrum leakage.The four window functions provided in the V93000 test system are analyzed.Due to the high frequency of the input signal,the fastest sidelobe attenuation window function is designed and the amplitude repair is completed.Add the window function to the test program and test the chip to be tested.The test results show that the ADC dynamic parameter measurement results are significantly optimized after the window function is added,and among all the window functions,the Flattop window function has the best optimization result for total harmonic distortion(THD),the 6 fastest sidelobe attenuation cosine windows have the best optimization results for signal-to-noise ratio(SNR),Signal to Noise plus Distortion(SND)and spurious-free dynamic range(SFDR).Although the optimized measurement results are within the measurement range specified in the chip manual,there is still a certain accuracy error in the SNR.Therefore,the Tabei&Ueda algorithm is designed for the optimization of SNR and the test program is completed.Create a new test item and associate the test program to complete the test.According to the test result,it is found that the SNR obtained by this algorithm is more accurate than the windowing function.In terms of test time optimization,this article designs two optimization methods.First,the4-FFT algorithm is used to process the sampled data to reduce the dynamic parameter test time.Firstly,determine the basic structure of the algorithm program by combining the 4-FFT algorithm;secondly,complete the writing of the algorithm program through C++;finally,use the new algorithm to replace the FFT algorithm in the traditional test program and complete the test.Through many tests,it is found that the introduction of the 4-FFT algorithm reduces part of the test time and does not affect the measurement results.Second,the SMC function is introduced into the test program to reduce the total test time of the entire test process.The SMC function needs to be used under the Smart Calc framework,and the test program written using the traditional universal test method is improved according to the Smart Calc framework.After comparing the results of traditional serial testing,multi-site testing and the introduction of SMC testing,it is found that the introduction of SMC testing can greatly reduce the test time.In the mass production test environment,when testing large quantities of chips,the introduction of SMC testing will make full use of the computer's multi-core and multi-thread functions,greatly reducing the chip test time and optimizing test costs.