Processing In-Memory Architecture Of MRAM And Bit Logic Operation Implementation Based On 2T-1MTJ Cell

The current mainstream Von Neumann processing architecture relies on the bus for communication between the CPU and the memory.The development of computer technology has continuously put forward higher requirements on the speed,read/write durability,integration,energy consumption and total capacity of the memory.Processing in-memory architecture embeds logic operations in the memory,which can significantly improve the data throughput efficiency between the CPU and the memory,and is expected to solve the "memory wall" performance bottleneck faced by the traditional bus architecture when dealing with data-intensive applications.The new non-volatile memory(NVM)has the advantages of high integration,fast access speed,low power consumption and unlimited read and write times.,and is more suitable for processing in-memory than traditional volatile memories(such as SRAM,DRAM,etc.)Spin transfer torque magnetic random access memory(STT-MRAM)is one of the new NVMs with broad industrialization prospects.In recent years,the design of processing in-memory baed on STT-MRAM has become a research hotspot,but this program still faces challenges in terms of computing speed and read-write reliability.Based on the STT-MRAM cell structure of 2T-1MTJ,this paper proposes a processing in-memory(STT-PIM)architecture that can work in conventional MRAM storage and bit logic operation modes.The main research contents include:(1)Combine the compact model that characterizes the characteristics of the MTJ device with the SMIC 40 nm process library for MTJ/CMOS hybrid performance simulation,and compare the writing characteristics of three common cell structures:1T-1MTJ,2T-1MTJ,and 2T-2MTJ,imulation results show that the 2T-1MTJ cell structure has more advantages in terms of area,writing power consumption and writing reliability.(2)Based on the 2T-1MTJ unit structure,this paper proposes a full adder module with integrated bit Boolean logic operations.The full adder can work in parallel logic operations and serial logic operations.Comparing the PIM architecture based on the above three unit structures,and analyzing the performance of its operating margin,timing length,hardware resources,etc.,it is found that the STT-PIM architecture proposed in this paper has the advantages of configurability,high density,and low power consumption.(3)The results show that the architecture can achieve fast parallel logic operations in a single read cycle.That is,at a clock frequency of 100 MHz,the solution takes 3cycles to execute a set of read and write operations and parallel bit logic operations.