The Study On Key Techniques For Achieving High Energy-efficiency On Emerging Non-volatile Memory Based Architectures

As the big data becomes pervasive,the massive amount of data have imposed great challenges on the underlaying storage system,in terms of high density and low energy consumption.On the other hand,as technology continually scales,the conventional SRAM and DRAM also face difficulties of building high density and low power memory arrays.Thanks to the non-volatility,high density,low leakage power consumption and good scalability,the emerging non-volatile memory technology has been intensively studied to replace both SRAM and DRAM for building massive capacity and energy-efficient computer system,including Resistive Memory,Spin Transfer Torque magnetic memory,and racetrack memory.However,introducing these technologies into current system also brings great challenges on design,since these technologies also come with unacceptable disadvantages,including long write latency and high write energy consumption.In order to make better use of these non-volatile memory technologies,this dissertation focuses on the unique features on non-volatile memory and also explore the architecture characteristics,and aim to study the key optimizing design on building high energy-efficiency non-volatile memory based computer system.The contributions and innovations are introduced as follows.(1)We propose to accelerate the ReRAM based memory system by leveraging the asymmetric crossbar structures.Recently,the resistive memory has been intensively studied to replace the DRAM on building the main memory system,thanks to its non-volatility,good scalability and high density.Because of the non-linearity of ReRAM devices,the ReRAM cells can be organized into crossbar structure to build memory arrays with even higher density.However,the asymmetric features of the crossbar structures has never been made use of before.In this work,we propose to leverage the access hotspots,to match by the asymmetric crossbar structures,by mapping the frequent access memory address into fast regions.We then propose both static an dynamic remapping scheme to adaptively remap the access addresses.The experimental results show that our proposed scheme can improve the performance of ReRAM based main memory up to 26.3%.(2)We propose to design to achieve high energy-efficiency on STT-RAM based GPGPU register file by leveraging delta compression.The STT-RAM memory technology has been intensively studied to replace SRAM on building GPGPU register file,since the SRAM face great problems of high leakage energy consumption as the process technology scales into sub-micron nodes.The existing design on STT-RAM based GPU register file still lack the capability of addressing the challenges of performance loss and extra energy consumption,imposed by STT-RAM.In this work,we propose to make use of the value similarity features on SIMT architecture,and employ delta compression algorithm to compress register values before writing them into STT-RAM based register file.We also introduce a centralized write buffer design to improve the utilization of the SRAM write buffer.The experimental results show that our proposed design can reduce the energy consumption of SRAM based design by 62.6%.(3)We propose a scheme to protect the STT-RAM based GPU register file against read disturbanceThought employing STT-RAM to build register file can acheive high energy-efficiency,as the process technology scales,STT-RAM memory cells face greate challenges on the read disturbance issue,which have seriously impact on the reliability of STT-RAM based register file.Directly apply existing solution on addressing the read disturbance issue to GPU architecture incurs severe performance loss and non-trivial energy consumption overheads.To address this issue,we propose to build compiler based algorithm to accurately identify dead read operations that can be shipped and do not need restore operations.In this way,both other performance and energy of the STT-RAM based register file can be optimized.(4)We propose to build energy-efficient racetrack based register files on GPGPU by leveraging a light-weight compression algorithmRacetrack memory has also been studied as a promising candidate to replace SRAM on building GPU register file.However,the required shift operations that need to be performed before reads/writes to align the data to the proper access port also result in excessive energy consumption and performance overheads.In order to address the issue of shift operations,we propose a light-weight compression framework to minimize the data amount that needs to be written into the racetrack based register file,by leveraging the SIMT architecture feature,value similarity.The experimental results show that the shifting data amount is significantly reduced and the energy consumption on shift operations is also effectively reduced.