A High-precision And Low-power MASH Structure Σ-ΔADC Design

In recent years,the development of the Internet of Things(Io T),biomedicine,and new energy technologies,there is a growing demand for high-precision,low-power analog-to-digital converters(ADCs)in fields such as industrial,medical,instrumentation,and sensing.This demand has grown exponentially in recent years,particularly with the unprecedented increase in demand for portable medical devices,battery monitoring,and data acquisition chips.For this type of low-speed signal acquisition,the primary performance requirements of the ADC are high precision and low power consumption.This paper presents the design of a high-precision,low-power Sigma-Delta analog-todigital converter(Σ-ΔADC)for detecting low-frequency signals.The Σ-ΔADC consists of three main parts: a Σ-Δ modulator,a digital decimation filter,and a digital interface.Firstly,based on the traditional multi-stage noise-shaping(MASH)structure modulator,the MASH modulator is improved by cascading a low-distortion Cascade of Integrators Feedforward(CIFF)twoorder modulator.The MASH modulator not only has the high resolution equivalent to the fourth-order modulator,but also has the low distortion characteristics of the CIFF modulator,which makes the loop finger process a small signal amplitude and reduces the modulator power consumption.Furthermore,a double-sampling structure integrator is proposed for the design of the modulator,which has a higher sampling frequency than the traditional integrator under the same sampling clock,thus reducing the power consumption of the integrator.Additionally,lowpower design structures are employed in other circuits,and the modulator is equipped with a clock and reference voltage circuit.The implemented modulator circuit achieves a signal-tonoise and distortion ratio(SNDR)of 115.8d B and an effective number of bits(ENOB)of 18.95 bits.The modulator consumes a total power of 3.15 m W under a 5V power supply.Finally,the digital decimation filter in this paper adopts the commonly used cascaded integrator comb(CIC)filter,also known as the sinc filter,in the Σ-ΔADC field.Based on the traditional CIC filter,a compensation filter and a half-band filter are cascaded to compensate for passband ripples and reduce the stopband frequency.The passband ripple of the digital decimation filter is approximately 0.004 d B,and the stopband attenuation is-114 d B.The digital interface adopts an IIC bus interface with low resource usage.The final Σ-ΔADC,has a SNDR of 112.1d B and an ENOB of 18.32 bits in simulation at a sampling frequency of 125 kHz.