Low-power Precision ?-?ADC Front-end System Research And Circuit Design

In recent years,the information technology digitization has developed rapidly,which increases the urgent demand for high-performance analog-to-digital converters(ADC)that as analog and digital interfaces.With its unique sampling mechanism and noise shaping method,?-? ADC has been widely used in the field of high-precision analog-to-digital.What's more,since it is easy to integrate as well as compatible with standard CMOS processes,the application area of ?-? ADC is constantly expanding.High-precision ADC play a crucial role for weak signal processing,such as seismic wave detection,military sonar detection and etc.The ?-? modulator is a key component in the high-precision ?-?ADC,which determines the ADC's performance.Therefore,in this thesis,we mainly focuses on studying the structure and circuits of ?-? modulator in the high-precision ?-?ADC.This thesis studies the principle and key technology of ?-? ADC,and deeply analyzes the characteristics and performance of ?-? modulators with different structures.According to the relationship between the performance of the sigma-delta modulator and the order of the modulator,the oversampling rate and the number of bits of the quantizer,we design a?-? modulator with fourth-order,128 times oversampling rate,and 2-2 MASH structure.By in-depth research and simulation to verify the impact of various non-ideal factors on the performance of the modulator,the design specifications of each module of the 24-bit high-precision ?-? modulator have been ensured.The design of the switched capacitor integrator,bandgap reference,operational amplifier and 4-bit quantizer in the ?-? modulator have been designed in this thesis.The structure and area of the two-stage operational amplifier art optimized,which helps to obtain higher gain,bandwidth and appropriate phase margin.For optimizing the structure of CMOS cascode bandgap reference source,we present a voltage compensation circuit to improves the anti-interference ability of the reference voltage.The dynamic latching comparator in the 4-bit SAR quantizer is optimized,whcih can achieve higher speed and sensitivity in the condition of lower power consumption.A digital-analog hybrid simulation is carried for verifying the system by using Spectre Verilog,and then the simulation output data is imported into MATLAB for analysis.The simulation results show that the modulator output signal-to-noise and distortion ratio(SNDR)is 149.7 d B.Finally,based on the TSMC 0.18 ?m CMOS process,we complete the layout design and post-simulation for the ?-? modulator.The layout area of the designed ?-? modulator is0.679 mm×0.7 mm,and its power consumption is about 16.4 m W.The post-simulation shows that the SNDR of the ?-? modulator is 142.6 d B and the effective number of bits(ENOB)is 23.4 bits.