Design Of Sigma-delta Modulator Based On 2-1 MASH Architecture

With the development of digital processing technology,higher requirements are put forward for Analog to Digital Converter(ADC).Sigma-delta ADC can provide highprecision data conversion,and has been applied in various fields,such as audio and video,radio frequency,etc.This paper studies the application of high-precision Sigma-delta ADC in audio field.Sigma-delta ADC can be divided into analog modulator and digital decimation filter.On the basis of studying the basic principle of Sigma-delta ADC,the system design of the modulator is completed at first.The system architecture of the modulator is MASH 2-1.Because of the noise leakage of MASH architecture modulator,the order of the first stage modulator is second-order and multi-bit quantization is adopted.In order to ensure that every integrator is not overloaded,a new set of modulator coefficients is calculated,which effectively improves the input dynamic range.Compared with other traditional modulators,the following techniques are adopted to improve the performance of modulators in the design of modulator circuits.By using bootstrap switch,the harmonic distortion caused by the nonlinearity of on-resistance of the switch is reduced.In the first stage operational amplifier,the chopper circuit is designed to filter the low frequency flicker noise and offset error of the operational amplifier.For the nonlinearity caused by mismatch of capacitor array in multi-bit DAC,the linearity is improved by using DWA correction algorithm.The digital decimation filter can reduce the oversampling rate of the modulator to Nyquist sampling rate,and also can filter out the quantized noise energy.In this paper,a three-stage digital decimation filter is designed,which achieves 25 times,2 times and 2 times lower sampling rate respectively.The amplitude-frequency response curve of each stage filter is given,and the code design of the whole filter is completed in Quartus environment.Finally,the hardware circuit of the filter is synthesized.The signal bandwidth of the modulator is 20 KHz and the sampling frequency is 4.41 MHz.The SMIC 0.18 um CMOS process is adopted in the design of the modulator circuit.The power supply voltage is 3.3V.The simulation results show that the SNDR of the modulator reaches 108.02 d B and the power consumption is 5.85 m W.The de-sampling rate of the digital decimation filter is 100,and the final output data frequency is 44.1KHz.