Design And Implementation Of SM4 National Secret Algorithm Simulation Program Based On SystemC

With the increasing complexity of chip design and chip integration,traditional design methods are inefficient when using HDL language to describe complex system design,because designers need to spend a lot of time and effort to convert algorithms from software implementation to hardware implementation.In order to solve these problems,SystemC as a system description language is proposed,which not only retains the language characteristics of C++,but also has the ability of hardware description.Using SystemC,a software algorithm can be easily implemented in hardware.The SM4 algorithm is a national secret algorithm independently designed by our country.It is a block symmetric cipher algorithm,which is widely used in encrypted communication and has high security.Based on the vehicle communication scene in the Internet of Vehicles,this paper uses SystemC to design and implement the simulation program of the SM4 national secret algorithm.It aims to study the different structures and performances of the SM4 IP core for hardware design,and it is expected to be integrated and used in a security chip and a cryptographic algorithm module in the HSM.This paper firstly expounds the research status of cryptographic algorithms and SystemC at home and abroad,then introduces the content of intellectual property IP,SystemC,simulation platform and SM4 algorithm in detail.Then taking the vehicle communication of the Internet of Vehicles as the application scenario,the paper clarifies the functional requirements and non-functional requirements of the system.These requirements provide guidance for the design and verification of IP cores.Then in the IP core design and implementation chapter,based on the SystemC design process,a behavior-level model was first established as a verification model.Then an RTL-level model was established on this basis to design various architectures of the SM4 IP core,including the basic loop structure,full pipeline structure,balanced structure based on circulation and pipeline.Finally,the IP core is simulated,verified and synthesized,and the five structures of the SM4 IP core are synthesized using the synthesizer.The performance of different structures is compared to obtain relevant data such as resource occupancy and throughput.The results prove that the designed structures all can work at a frequency of 100 MHz.The throughput of the full pipeline structure reaches about 1.32 Gbps,and the throughput of the basic loop structure reaches about 420.36 Mbps.The full pipeline structure exchanges 4.85 times resource consumption for a 31.29 times increase in throughput.The simulation program designed for the SM4 algorithm in this paper has been developed and tested,and it meets the expected results.