Implementation Of SystemC In The AES Algorithm IP Core Design

In this paper, we use the newly come out system level description language, SystemC, to design an IP Core based on AES encryption algorithm. Studying the subject, in the IC design field, especially in the middle and small scale IP Core design, the differences between using SystemC and traditional C language in system design flow, the problems we maybe meet, and the new conception and changes SystemC has brought in the SoC era. The studying here just limited in the conversion from system design to RTL design, regardless of how to do RTL design, verification and even the co-design of software and hardware with SystemC.In the design process, we use Top-Down design flow to achieve the architecture and all sub-modules design. SystemC and C are introduced at system level, Verilog HDL is used at RTL level. The finial design can achieve both encrypt and decrypt functions with all the three different key length. Also, base on FPGA platform of Stratix II, with the integrated design tool Quartus II5.0, we achieved design compile, place& route and post simulation.In the later, we hope to establish a practical platform based on the above work and find out a new way to use SystemC effectively in the system design of IP Core design field and conversion to RTL, shorten the design circle and promote efficiency.