| With the rapid development of artificial intelligence,big data and cloud computing applications,the traditional von Neumann architecture computer,which transmits data through the narrow bus structure between the processor and the memory system,has been unable to meet the frequent memory access requirements of data-intensive applications,resulting in the "memory wall" problem which seriously restricts the improvement of system performance.In order to solve this problem,researchers have introduced new technologies and architectures,among which,"processing-in-memory" minimizes the change of standard memory modules,becoming one of the hot research fields in the direction of "logic-in-memory".Based on SEDRAM devices with Hybrid Bonding 3D integrated technology,a high-performance memory controller is designed in this thesis for continuous intensive memory access in DRAM"processing-in-memory" scenario.By analyzing the application scenarios of the "open-page" and "close-page" memory access strategies,the thesis draws the conclusion that "open-page" is suitable for high-frequency continuous memory access scenarios,while "close-page" is suitable for low-frequency random memory access scenarios.In addition,a consistency scheme based on register cache is designed by taking advantage of the locality of data in DRAM pages,which can reduce the read access latency of 89.2%and write access latency of 94.1%at most.In order to further expand the application scenarios of DRAM "processing-in-memory" system,an adaptive memory controller is designed based on the advantages of different cache management strategies,which can flexibly control the switch state of DRAM memory pages according to the application scenarios.The "open-page" memory controller with cache consistency design has been successfully applied to the DRAM "processing-in-memory" chip,and the logic chip will be taped out on the SMIC 28 nm process line.Aiming at the typical data intensive application "GEneral Matrix-Vector multiplication(GEMV)",this thesis designs the Cache-major scheduling strategy,a hardware and software cooperative optimization scheme,by deeply studying the spatial locality of DRAM memory pages.Compared with the conventional memory address mapping scheme and the "Page-hit oriented" scheduling strategy,the memory access bandwidth of the memory control system using Cache-major scheduling strategy increased by 95.7%and 28.8%,respectively,in the face of large-scale GEMV problems(@511×255).Compared with NVIDIA GTX280 GPU,this system has certain advantages in single-core memory access bandwidth and algorithm execution time.Ferroelectric RAM(FeRAM)uses ferroelectric thin film as memory material to avoid periodic refresh operation of memory cells,and has lower power consumption,higher stability and longer data retention time than DRAM devices.Therefore,FeRAM is expected to replace DRAM devices as a new memory medium for"processing-in-memory" systems in the future.In this thesis,a memory control system based on FeRAM is designed,and its occupied resources,power distribution and memory access performance are tested and evaluated in detail on the FPGA platform.This study is expected to promote the application of memory controller based on new memory devices in "processing-in-memory" system. |
