Research On Graph Processing Acceleration Mechanism Based On High Bandwidth Memory

Under the background of information age,Graph Processing has been widely used in various realistic scenarios,such as commodity recommendation,social network,financial risk control,network security and knowledge graph.With the arrival of 5G era,the scale of graph data is showing explosive growth,so it is particularly important to improve the performance of graph computing.In addition,because of the rapid development of graph computing system,far more than the common memory,so the system performance is often limited by memory,and high bandwidth memory is one of the effective strategies to break through this limitation.Although high-bandwidth memory has advantages such as high bandwidth,high efficiency and low power consumption,the switching architecture adopted by high-bandwidth memory to achieve global addressing will affect the utilization of bandwidth.Therefore,how to realize the full utilization of high-bandwidth memory and improve the graph computing performance is still one of the main challenges facing this field.In order to improve the bandwidth utilization rate of high bandwidth memory in graph computing system,this paper proposes a memory access optimization strategy and applies it to a general graph computing system.Based on three-layer Clos switching network architecture,this strategy adopts fixed route orthogonal link scheduling algorithm,which can make full use of high bandwidth memory while having global addressing function,and has simple module design,less resource consumption and better scalability,so that it can support more parallel processing units.When the strategy is applied to graph computing system,the impact of high bandwidth memory read and write delay is reduced by using burst transmission,the memory access efficiency is improved by using bitmap,and the parallelism is improved by using multiple processing elements and HBM’s pseudo channels.In this dissertation,the breadth-first algorithm and web ranking algorithm are tested experimentally in graph computing systems using different memory schemes.The experimental results show that the test performance of the two graph algorithms in the graph computing system using a single HBM stack is improved by 5.91-6.02 times compared with that of DDR.The performance of global addressing mode is 4.15-4.48 times better than that of DDR.The bandwidth utilization of scheduling optimization schemes is 1.32 to 1.45 times higher than that of global addressing schemes.