Research And Application Of DRAM Electrical Stress Burn-in Test

With the development of advanced integrated circuit manufacturing processes,the size of Dynamic Random Access Memory(DRAM)has become smaller and smaller,and its overall performance has been significantly improved.As a follow up to this,numerous application situations have emerged,and the use of technologies such as big data and cloud computing has started to become more widespread,demanding higher reliability of DRAM chips.At this stage,the stability and high availability of DRAM chips has become a key indicator for all industries,especially in the fields of aerospace,medical devices,large-scale mechanical manufacturing,big data,and cloud computing.The burn-in test is the key step to guarantee that these key indicators meet the requirements,but at present,it is still a difficult task to design the best DRAM burn-in test plan according to different application environment.In the thesis,we analyze the failure mechanism and failure model of DRAM,establish a specific certain general DRAM burn-in test platform,and select the corresponding electrical and thermal stress based on this platform to design and perform a customized burn-in test scheme for conventional DRAM chips.The major work of this thesis is as follows.(1)The DRAM burn-in test platform was designed and built.The advantages and disadvantages of the available system solutions are compared and analyzed,and the application-based burn-in test system is selected by comparing the operability and generality of the solutions.The overall composition structure of the system is designed,and the hardware equipment is selected for the electrical stress requirements of the test generation.The burn-in room is designed and optimized,and the temperature control system of the burn-in room is realized.Controllable temperature of 130℃ for full load operation and up to 180℃ for high temperature storage.For the algorithm problem of the test software,the failure model of DRAM failure is established,and the test algorithm with high fault coverage rate and low time cost is selected to apply specific practice.Based on this system,functional test steps and read/write stress test steps are designed respectively.The construction of a test platform with high operability and low implementation cost was finally completed.(2)The evaluation of the burn-in test system was completed.Through the burn-in room temperature stability and thermal balance evaluation,the read/write stress test time stability evaluation,and the error reproducibility evaluation,the completed burn-in test system was tested in all aspects to ensure the stability of the test system and the reliability of the test results.It also provided a highly implementable and optional evaluation solution for the evaluation of burn-in test systems for other types of chips.(3)The design and implementation of the specific burn-in test program were completed.Customized design of test items,test stress level,test duration,failure judgment,and test item sequence.The burn-in test experiments were conducted according to the customized process.The final number of qualified chips was 967 and the number of failed chips was 36.The data obtained was analyzed,and the chip life of the batch was evaluated based on the test data.The final predicted life span was 13.45 years.Additional test items were done and analyzed for some failed chips.A complete and effective burn-in test solution was finally provided by optimizing the process.After 10 months of operation,the failure rate of the chip particles that passed the test was 0 after feedback from the user.