Development Of Ultra-high Performance Stacked Gate-all-around Nanosheet Field-effect Transistor

With the continuous development of integrated circuit（IC）along with Moore’s law,the traditional MOSFET needs lower power consumption at the same time of smaller size and higher speed.Vertically stacked gate-all-around nanosheet field-effect transistors（GAA Si NSs MOSFETs）are considered to be one of the most promising candidate device structures for the 3 nm and blow technology nodes due to its high integration density,low performance in short-channel effects（SCEs）,high performance and design flexibility in circuit applications.However,stacked GAA Si NSs devices also face severe challenges in manufacturing,such as insufficient device performance,difficult release process of highly selective Si NSs channel,complex inner side process and difficult low-temperature integration process.Therefore,in view of the poor driving performance of GAA Si NSs device,this paper adopts landing pads（LPs）and multi-channel technology to improve the performance of GAA device.In order to reduce the high parasitic resistance of devices and increase the device driving current,LPs technology compatible with mainstream GAA devices was introduced to improve the device driving performance.The LPs technology is a nanoscale Si Nx sidewall obtained by SIT,then a set of lithography plates are added and a high-efficiency hybrid lithography and ion etch process is used to obtain nanoscale Fin and large-size LPs structures.The large size LPs structure can be used as source and drain（SD）to increase the contact area between SD and metal.The simulation results show that the LPs technique can effectively improve the device driving performance.In order to solve the problem of insufficient driving current of low-level NS devices,multi-channel technology is introduced which uses multi-layer stacking to increase the carrier concentration of the device channel and increase the device driving current.In this study,a10-layer channel device was simulated by TCAD software and simulation reveals that multilayer NS channel technology can increase the driving performance of the device and the short channel effect of the device is not affected.Compared with 3-layer n/p-type GAA Si NSs,10-layer NS-channel n/p-type devices drive more than about 1.5 times higher current than 3-layer devices,and the SS of n/p-type devices is about 67.2 m V/dec（67.5 m V/dec）and DIBL is 3.85E-02 V/V（2.53E-02 V/V）.The driving current(I_ON)of n/p-type devices with LPs technology is increased by about1.5 times and a subthreshold swing（SS）of 66.49 m V/dec.Besides,GAA devices with LPs technology are fabricated and analyzed for device characterization in this paper.The experimental results showed that the parasitic resistance of GAA devices with LPs structure is reduced by 99.8%and the drive current of n/p-type GAA devices is increased by 3 times and2 times,respectively.7-layer stacked GAA Si NSs MOSFET devices were fabricated on bulk silicon substrates in this paper.The device fabrication process is compatible with the current mainstream GAA NS MOSFET preparation process,but some key of process modules needs to be optimized.After process optimization,7-layer NS channel devices can achieve drive current to the m A level,which is about an order of magnitude higher than 3-layer stacked GAA Si NSs devices.The 7-layer NS-channel n-type GAA MOSFET achieves a drive current of 1.5E-4 A/μm（9.26E-5 A/μm）,SS of 72.97 m V/dec（72.59 m V/dec）,and reduced DIBL of 18.65 mV/V（12.27 mV/V）.