The Study And Implementation Of Asynchronous RSA Cryptographic Algorithm Chip

With the rapid promotion and application of information technology and Internet communication technology,the development of communities is increasingly dependent on informatization,so it is particularly important to protect the security of information.Cryptography is the core technology and basic support for ensuring network and information security,and plays an irreplaceable role in maintaining national security,promoting social and economic development,and protecting the interests of the people.The RSA cryptographic algorithm,as a popular public key cryptosystem,as long as the key is long enough,the information encrypted cannot actually be cracked,so it is widely used in lots of scenarios with high requirements for communication security.Compared with the software method,the hardware which implements the RSA algorithm has the advantages of faster speed and higher security.Currently,the RSA cryptographic algorithm chips available are mainly implemented by synchronous integrated circuits technology.Although the synchronization mechanism simplifies the chip design flow,it also brings a regular clock analysis reference.The power analysis attack technology can easily crack the synchronous circuit,so a circuit mechanism that can get rid of the clock reference is more valuable.The clockless asynchronous circuits use an event-driven handshake mechanism to transfer and synchronize data,which has natural advantages in the face of power analysis attacks.Therefore,it is very meaningful to study cryptographic chips based on asynchronous mechanism.This paper comprehensively studies the RSA cryptographic algorithm and its asynchronous implementation.We harness the BBD asynchronous circuit mechanism to realize the RSA security algorithm.Firstly,through an in-depth understanding of the working principle of the RSA cryptographic algorithm,we analyzed the key features of the hardware implementation of the RSA algorithm chip and its security protection strategy.And it is concluded that the implementation of the BBD asynchronous mechanism is one of the effective methods to solve the safety problem.In addition,combined with the BBD asynchronous circuit mechanism,the core algorithm of RSA,namely the CIOS modular multiplication algorithm,has been improved to enhance the encryption and decryption performance of the chip.Then,the micro-architecture of our asynchronous RSA crypto chip is presented,using the I~2C serial bus protocol as an interface to ensure normal communication to outers,and the circuit implementation and verification of the overall algorithm are completed on a FPGA development board.Finally,the asynchronous RSA cryptographic algorithm circuit is transplanted to ASIC,and the whole ASIC design process including synthesis,formal verification,placement and routing,parasitic parameter extraction,timing analysis,layout verification and before and after simulation is completed based on the SMIC180 technology.According to the experimental test results,our chip owns good performance.The equivalent gate number after placement and routing is about 195K gates.At an equivalent average operating frequency of 332MHz,the time to perform a 1024bit encryption and decryption operation is about 52ms,and the average power consumption is 26.9m W(of which the power consumption of the synchronous I~2C circuit accounts for 71.20%).