YHFT-XDSP CorePac L2 Controller DMA Logic Design And Verification

DSP is widely used this information era, and the DSP technology is mature gradually. The On-chip memory is an important part of DSP, its performance is crucial to DSP performance. At present the On-chip memory of DSP has the following characters: 1. Cache + RAM structure; 2. Two level memory structure; 3. A larger memory size; 4. Complex memory functions. This dissertation focuses on the DMA-treating logic in L2 controller which handles the DMA requests to the L2 SRAM. The main researches and contributions of this dissertation are as follows:1. According to the characters of the YHFT-XDSP L2 memory and the DMA transfer, pipelined technology is used to implement the DMA control logic in L2 controller, the pipelined technology improved the process speed and the frequencies when L2 SRAM responded to the DMA request.2. Combined with the DMA access pipelined technology, the Shadow Tag technology reduced the time cost of the operation to keep the data coherence between the L2 SRAM and the L1 D Cache when DMA request L2 SRAM.3. The Memory Protection mechanism and the Error Detection and Correction mechanism are designed in L2 SRAM controller, thus the data control ability and the system safety is enhanced when the chip dealed with a complex application and the adaptability of the chip it broadened.4. The functions mentioned above are implemented with Verilog HDL language and are verified on module level verification and system level verification. Compared with the non-pipelined implementation, the pipelined design has got obviously performance improvement for all kinds of DMA requests.