FPGA-based PageRank Acceleration Technology Research

The PageRank algorithm is widely used in real-world scenarios such as the World Wide Web and social networks.However,due to irregular memory access,it is usually inefficient when performing graph calculations.The most important core affecting its computing performance is the sparse matrix-vector multiplication unit.FPGA reconfigurable computing system has great potential in accelerating matrix computing.Therefore,this paper combines PageRank algorithm and sparse matrix-vector multiplication algorithm to study hardware acceleration technology based on FPGA platform,and explores a high-performance,low-power consumption algorithm.Sparse matrix and PageRank algorithm accelerator.The main work of this paper is as follows:First,the calculation method of PageRank is studied,and the characteristics of the hardware acceleration platform are compared and analyzed.On this basis,the calculationintensive unit sparse matrix-vector multiplication operation is optimized.In terms of throughput,area,and delay,the sparse matrix-vector multiplication is calculated.The data transmission structure is designed,and two optimization algorithms are proposed.Secondly,the power iteration method of two-step operation SpMV is proposed.The hardware part designs the off-chip communication module and the power iteration overall architecture.At the algorithm optimization level,the aggregate discrete model is used to complete the realization of system-level functions.Finally,the hardware acceleration system is constructed by means of software and hardware collaboration,and the test and verification are carried out on the "ARM+FPGA"SoC architecture.The architecture completes the acceleration of the algorithm in the FPGA part,and completes the control of the system in the ARM part.The results show that the on-chip resources consumed by the architecture proposed in this paper are in line with the expected results,and the calculation results are highly accurate.For mediumsized matrices,the acceleration effect of the FPGA accelerator in this paper is obvious,and the computational efficiency of sparse matrices is as high as 90%.The optimized PageRank algorithm can achieve an average speedup of 10 times.