Design And Research Of FPGA-based Deep Learning Accelerator

At present,deep convolutional neural network(CNN)has been widely used in computer vision applications such as target tracking,gesture or face recognition.However,the implementation of most existed deep learning applications is based on high-power graphics processing unit(GPU)platform for accelerated computing,which limits the wide application of convolutional neural networks.Field programmable logic gate Array(FPGA)has the characteristics of high efficiency parallel computing capability,flexible configurable and low power consumption,which makes it an ideal accelerated computing device with small,efficient,flexible and powerful performance to apply CNN-based solutions to embedded systems such as robots,drones and wearable devices.By building a customizable accelerator architecture in FPGA,the computing power required by CNN can be provided within the size and power consumption range required by the application.Therefore,deep neural network acceleration based on FPGA has become a hot topic in current research.In order to improve the inference performance and efficiency of deep convolutional neural network,this paper mainly focuses on the design and optimization method of multi-scale convolutional neural network accelerator based on FPGA.A multi-scale optimization design method from the aspects of network model topology,computing cycle and hardware resource balance was proposed and a binary VGG network accelerator based on data flow architecture was realized and verified by the CIFAR-10 dataset scaled to224×224 size.Experimental results showed that binary VGG network accelerator based on FPGA platform reaches 81% accuracy,219.9 FPS recognition rate and the accuracy compared to the software training results fell by 1%,but the highest recognition rate was promoted 33 times than the same type of VGG accelerators.Furthermore,the multi-scale optimized design of the deep neural network accelerator method was applied to the license plate recognition system.An end-to-end license plate recognition network model called BLPR based on the binary neural network of 96×32was designed.And the method combining software and hardware was adopted to construct the end-to-end license plate recognition system based on FPGA.The accelerator of BLPR was optimized by the multi-scale optimization method proposed in this paper,which achieved high speed license plate recognition application on FPGA.The system was verified by the Chinese City Parking Dataset(CCPD)and achieved 98.1% accuracy on the general processor platform,96.7% recognition rate on the FPGA platform,and the recognition speed up to 3.74 K FPS.The experimental results implied that the BLPR was better than the similar methods and achieved higher robustness and recognition speed than the traditional recognition methods.