Design And Application Of Configurable High-level Synthesis Functional Library Based On FPGA

With the development and arrival of various new CPUs,the computational performance and efficiency of computers have increased dramatically.However,the physical performance of semiconductor technology is limited,and it can not meet the demand of CPU computing capacity for the continuously increasing amount of data.In the 21 st century,with the increasing performance of new processors and electronic devices for specialized computing such as Graphics Processing Unit(GPU)and Field Programmable Gate Array(Field Programmable Gate Array),heterogeneous computing began to become an effective way to improve computing performance,and gradually became a major player in the field of High Performance Computation(HPC).FPGA is playing an increasingly important role in heterogeneous computing,but the register transfer level design flow is not only inefficient,but also requires designers to be familiar with the circuit structure.High-Level Synthesis(HLS)allows developers to design FPGA circuits more efficiently with a more familiar programming language and a higher level of abstraction.When using HLS tools(such as Xilinx Vivado HLS),specific design patterns and techniques(incorporating pragma instructions)are required in order to create highperformance circuits.In addition,designing efficient concurrency and data flow structures requires a deep understanding of the hardware and undoubtedly imposes a higher learning cost on the programmer.In regarding to this issue,this paper proposes a set of functional concurrent programming paradigms,implemented by C++ templates,which can quickly implement high-performance parallel pipeline computing models on FPGA by adjusting predefined parameters.The use of this pattern library can be flexibly adapted to the parallel structure and streaming structure in the algorithm,which greatly improves the coding efficiency.And where functional languages are inherently more suitable for high-level hardware generation because they have limited functional side effects.And by describing the data flow more naturally,each function module can be directly mapped to the hardware pipeline.In this paper,we further use the proposed library of functions optimized for implementation on FPGA based on the features of Quantum Particle Swarm Optimization(QPSO)algorithm.The contribution of this paper is as follows:(1)Parallelization analysis of HLS functions,using functional programming to propose four design concepts of general parallelization operators based on common parallelization models,and a high-performance computing model based on C++templates for hardware generation strategies are proposed.High-performance algorithms can be implemented on FPGA with high generality by fixing only a few simple parameters;the four operators are Tree OP,Map OP,Zip With OP and Reduce OP.For the case where increasing frequency leads to some complex computation time exceeding the current clock cycle,this paper proposes a long pipeline structure improvement method for the Reduce operator.(2)The implementation of the QPSO on FPGA is optimized using the functional library proposed in this paper.Due to the large scale and intensive computational characteristics of the particle swarm algorithm,this paper unfolds the particles by groups,analyzes the data flow according to the computational model and performs targeted optimization of the FPGA implementation.The results show that QPSO on Xilinx Kintex Ultrascale xcku040 achieves an acceleration ratio of up to 123 times compared to Intel Core i7-6700 CPU;in addition,the design and implementation of vector distance sum-of-squares function,the algorithm is implemented in only one line of code,and the experiment analyzes the impact of each parameter on the generation of hardware structure,which in turn drives the reason for the change in hardware resource usage.