Research And Design Of Operation Path Of A Special 32-Bit Fixed-Point DSP Chip

In recent years,with the continuous development of integrated circuit industry,digital signal processor(DSP)is widely used in communication,consumer electronics,aerospace,national defense and military,and are incressingly favored by people in the IC industries,and a superior performance of DSP can not be separated from its CPU powerful computing capability support.Based on the national defense scientific research project as the background,this thesis according to the special application of the project,around its working frequency,area and other requirements,a 32-bit fixed-point digital signal processor BMDSPF32 operation path related unit is studied and designed,including:multiplier,arithmetic logic unit(ALU),shifter,adder,pipeline and other related units.The DSP system,special instruction sets and pipeline are designed to guarantee the premise for the operation unit to process data.The special instruction sets can accommodate 16 or 32bit wide instructions.Although the complexity of instruction decoding is improved to a certain extent,it can more flexibly adapt to the requirements of various instructions to complete more complex operations.In the eight-level pipeline designed in this thesis,the three steps of instruction fetching,decoding and reading are divided into two steps each,making the pipeline operation more stable and smooth,and the progression of the pipeline for different instructions will change accordingly,which further improves the performance of the system.Adder is the basis of multiplication.By comparing Serial Carry,Carry-Select,Carry-Save and Carry-Lookahead Adder,this thesis designs an addition algorithm combining Carry-Save and optimized Carry-Lookahead,which makes the speed and area meet the design requirements.The multiplication and accumulation operation of the multiplier is one of the important indexes to evaluate the performance of DSP.The 32×32 bit multiplication designed in this thesis uses four 16×16 bit multiplication units to carry out separate operations,and then uses accumulative operations to get the final result.According to the operation law of multiplication and the distribution law of partial product data,the connection operator in digital IC design is used to connect different bits of the result and then add them up.In the whole operation process,a 64-bit wide adder is reduced and an other 64-bit wide adder is improved to a 48-bit adder.Not only the addition complexity is reduced to speed up the operation,but also the overall area is reduced by more than half.Through the study of array multiplier,tree multiplier and the various compression and coding algorithm of multiplier,the internal structure of 16×16 bit multiplication design as a kind of modified tree multiplier,tree multiplier of the longest path carry chain uses an optimized Carry-Lookahead Adder,make the output of each delay control in the same range,which is balanced in speed and area.After studying the advantages and disadvantages of multipath selective switch shifter,logarithmic shifter and barrel shifter,an improved barrel shifter is designed in this thesis,which is more flexible and easy to control than traditional shifter.After the adder,multiplier,the shifter design is completed,the Arithmetic logic unit(ALU)is also optimized.At the end of the design,the simulation verifies the relevant modules of the instruction and operation path,and carries out the synthesis,formality verification,post-synthesis simulation,test coverage collection,LVS verification and layout design.The results show that the clock frequency reaches 150MHz and the area is 41.32 mm~2 under the0.18μm process of TSMC.The system performance meets the requirements,and has been tape out successfully.