Multi-channel Fft Processor Multiplier Reuse Research And Design,

With the rapid development of microelectronic technology, complex digital signal processing technology is being applied in various fields, and it is increasing widely employed in the field of communication, of which FFT algorithm has become an integral part. In recent years, high-speed and real-time is becoming more important in communication, so integration of OFDM and MIMO is a trend in order to meet the increasing needs of communication, for that OFDM can increase spectrum efficiency and MIMO can improve system capacity several times. Due to the integration, research on FFT moves from single-path FFT toward configurable multi-path FFT, and the latter has been applied in many communication protocols, such as LTE.In this thesis, detailed research on FFT processor is done at algorithm and structure level. Study on algorithm is very mature and difficult to reach a breakthrough, so FFT processor is studied in this thesis from the aspect of structure and implementation. Features of different FFT processor constructions especially pipeline--MDC and SDF, is studied combined with algorithm. To meet the application of low area, the SDF structure has been optimized and two low-area FFT structures are proposed, referred as structure A and structure B. Structure A is based on radix 24 while structure B on raidx-8 and radix-16. Although based on different algorithms, they both share trivial multiplier through data flow controlling strategy, which can increase multiplier utilization, reduce the number of used multiplier, resulting in reduction of area and power consumption. The comparison among the two structures and other typical structures are given in this thesis.Configurable FFT processor in LTE is designed based on structure B and appropriate algorithm according to LTE protocol. The entire processor design has been divided into two parts---control flow and data flow, so that implementation and debugging would be easier. Data flow works in frequency of 30.72MHz, and major part of memory works in synchronous frequency 122.88 MHz. In order to guarantee function and reduce area, memory is split and merged reasonably and appropriate types of RAM are selected, resulting in that RAM utilization increased, RAM reused and chip area reduced. Twiddle factors are expressed by 1/8 domain, so factor utilization increases and ROM area is reduced. A low-area FFT proces?or used in LTE has been proposed with good configuration, not only in length of FFT according LTE protocol but also in SNR and power consumption.A testing platform is built using FPGA development board, and the proposed configurable multi-path FFT processor used in LTE is implemented, verified and tested. The test of the FFT processor implemented in Xilinx development board was passed finally.