Design And Verification Of DDR4 Write Buffer In A Special Application Scenario

With the development of semiconductor technology,the integration of chips is getting higher and higher,and the running speed is getting faster and faster.However,there are imbalances in the development of storage systems and the development of processor core computing speeds.Therefore,the buffer circuit is indispensable at the data transfer portion where the clock rate is different.How to design a suitable snubber circuit,while maximizing system performance without consuming a lot of resources is a very difficult problem in ASIC design and processor design.The access speed of a dedicated chip can largely affect the overall performance of the chip.How to deal with the speed gap between the storage system and the processor is a key point in ASIC design.1.Researched the memory controller design and DDR4 technical manual,compiled the DDR4 write characteristics,and analyzed the similar buffer circuit design,and proposed the classification buffering idea to improve the write bandwidth utilization.2.According to the requirements of system design,several aspects of data preprocessing,classification,arbitration and asynchronous handover are studied,and the data is classified and buffered.The hardware description language is used to complete the design of the whole circuit.The basic knowledge points of the design are studied,such as synchronous FIFO,asynchronous FIFO and multi-input and single-output FIFO.The design of the buffer is studied,including buffer depth,width and address management.The size of the buffer is theoretically determined.Multi-channel arbitration is studied,and stack-based arbitration and matrix arbitration are implemented.The algorithm used in multi-channel arbitration is selected by algorithm comparison and implementation difficulty.3.Finally,UVM verification is carried out on the design,and the corresponding verification environment is built.The test is continuously improved by directional excitation and random excitation.The detection points are collected to collect data,and the file comparison method is used to check the error.Finally,the correctness of the code and the input and output data are verified.Not lost.The design is applied to an ASIC chip to achieve an overall memory access improvement without any errors.The classification buffer circuit can provide a new idea for the buffer design.When using IP,you can study the characteristics of IP and combine some external circuit design to maximize the performance of IP.This design can not only play a buffering role,coordinate the internal and external write rates,but also maximize the performance of DDR4.It is a very important part of a dedicated chip design.