High-performance Cache Design Of Secure SoC Chip

With the acceleration of informatization in all walks of life,the issue of information security has become an important issue that cannot be ignored.As a key part of information systems,security chips are widely used in vehicles,mobile devices,military and other industries.Cache technology is a key technology used to solve the problem of speed matching imbalance between CPU and main memory.In a secure chip,how to design a secure cache that takes into account both data security and high-performance memory access capability is a difficult point.The Cache researched and designed in this subject is based on a secure SoC chip.This paper introduces the basic storage structure and Cache principle,analyzes the security problems of the embedded system in detail,and gives the security solutions at the module level and the system level.On the basis of ensuring security,this paper also optimizes the performance of secure Cache through various methods.For example: optimize the hardware implementation of the security encryption algorithm;design a special cache structure inside the Cache;design a special prefetching mechanism according to the characteristics of the bus and processor.Finally,the design of a high-performance secure cache with good application value is realized.This paper summarizes the research status of Cache at home and abroad,and analyzes the key technical nodes of Cache technology and the main problems it faces in security chips.The working principle of Cache and common embedded software attack methods are analyzed in detail,which provides theoretical support for the design of secure Cache and the security architecture of chips.At the same time,the common means of improving Cache performance are analyzed,and the processor and bus timing used in this design are analyzed to provide theoretical support for the performance improvement of secure Cache.According to the actual needs,the Cache designed in this paper adopts the Haval structure in the storage structure,with a total capacity of 64 KB.It adopts a four-way group associative mapping mechanism,and supports configurable cache area and DMA mode data access.In order to ensure the security,this paper presents the module-level and system-level security schemes.In terms of Cache security,technologies such as AES encryption algorithm,CRC check algorithm and address association are used to deal with common software attacks.In terms of system security,MPU modules,random waiting arbiters,etc.are used to deal with side-channel attacks.In order to improve the performance of Cache in security scenarios,the instruction cache and data cache are optimized respectively.On the instruction cache side,combined with the timing characteristics of security encryption and the timing characteristics of AHB bus,a new prefetch scheme and prefetch strategy are formulated,which improves the prefetch hit rate and reduces the cost of read misses.At the same time,the branch jump indication signal given by the processor is used to predict the jump behavior,and the data that jumps during prefetching is refined,which reduces the number of invalid prefetches and the time of repeated decryption.On the data Cache side,data synchronization is realized when plaintext and ciphertext coexist internally,and it is not necessary to flush out the external memory and then read back and decrypt,which improves the cache performance.Some special cache structures are added to the instruction cache and the data cache,and are controlled by different state machines.The hardware implementation of the Advanced Encryption Algorithm(AES)is optimized.By registering the intermediate results of the round key and using pipeline processing during decryption,fast AES decryption is realized,and the impact of the security module on the system performance is reduced.This design adopts the bottom-up design method and uses the hardware description language to complete the code writing.Finally,the Cache part is simulated and tested and synthesized.Detailed verification is carried out in the module-level simulation to ensure that the functions are correct,and the coverage and other indicators meet the requirements.In the system simulation,the Cache was tested in various modes,and the Dhrystone program was used to test the performance of the designed modules.Finally,it was found that the addition of functions such as prefetching in the safe mode improved the performance by about 8.01%,reaching a Default target.Finally,the DC tool is used to synthesize the Cache,and the secure Cache meets the design requirements.