Hardware Implementation Of The Encryption In Security Layer Of Communication Terminal

With the rapid development of electronic information industry, wireless communication technology brought convenience to people’s life and work. People, however, at the same time of enjoying the wireless network bring convenience, also brought under its own defects in imperceptible- security matters.As is known to all, the IEEE working group set up a security layer in Wi MAX protocol to solve such problems, security layer by AES algorithm and the CMAC, CCM mode combination of complete data confidentiality and authentication work.Security layer data processing operation in complex and CPU are processed to complete communication systems related tasks, scarce resources for security layer, so the security layer of data processing need hardware to reduce the computational load of the CPU, which should be reasonable use of hardware circuit, effectively achieve the communication terminal security layer encryption algorithm.In this paper, in-depth study and analysis of Wi MAX, the structure and security layer protocol data unit of the agreement and the bus architecture of ARM, the hardware of the encryption algorithm. First of all, the analysis and comparison of CCM mode, the CMAC model, implement CCM mode and the CMAC model of hardware circuit.AES-CCM mode is based on two block encryption algorithm of encryption mechanism: one is the CTR(counter) model, and the other one is CBC- MAC(encrypted block links authentication codes) algorithm.And AES- CMAC model based on symmetric key block cipher is a hash function, provides the ratio test and/or error detection code more robust data integrity protection. Secondly, this paper designed the hardware accelerators to adopt the CCM mode treatment protocol data unit and adopts the model of CMAC signaling. In such aspects as structure, electrical hardware accelerators from structural, electrical, etc into the dual port RAM, descriptor FIFO, control logic and encryption hardcore, from the five modules such as device interface.Encryption hardcore is the key to the security layer algorithm module, its function is based on external control logic input initial key, the data and some parameters for security of the data processing.Encryption hardcore is mainly composed of four parts, respectively is authentication module, hardcore control module, key extension module, encryption module(including CMAC neutron key generation logic).Through this several modulescan in CCM mode is produced in the process of cipher and encrypted authentication codes, the CMAC model was produced in the process of authentication codes.Again, in order to reuse as the target, discussed the AES algorithm, realization of data path for 32 bit AES cores.Finally, this paper USES hardware description language(Verilog), hardware accelerators for the register level description.Bottom-up is studied by using EDA tools, logic simulation validation strategy, first sweeping validation of each module, and then to system level integration design validation.To build the FPGA verification environment and design verification, particular way is the use of FPGA supporting software tools(ISE) integrated the FPGA configuration file, and then through the FPGA provides the JTAG mouth will be downloaded to the FPGA design;For chip firmware through debugging PC software, download for the processor to take to the specified storage refers to perform. And statistics of the key modules of FPGA resources occupied.Simulation and verification results indicate that the design is correct.