Investigation Of Compact Hardware Implementation Of Advanced Encryption Standard

A compact, efficient and highly reliable implementation of the Advanced Encryption Standard (AES) is the desirable encryption core for any practical low-end embedded application. In this thesis we design and implement a compact hardware AES encryption and decryption system.We investigate various architectures for compact AES implementations in 0.18 μm CMOS technology. We first explore a new compact digital hardware implementation of the AES s-boxes applying the discovery of linear redundancy in the AES s-boxes. Although the new circuit has a small size, the speed of this implementation is also reduced.Encryption architectures without key scheduling that employ four s-boxes and only one s-box are implemented using the new AES s-boxes, as well as based on other compact s-box structures. The comparison of the implementations based on different architectures and s-box structures indicates that the implementation using four s-boxes based on arithmetic operations in GF(2~4) has the best trade-off of area and speed. Therefore, using this s-box implementation, a complete encryption-decryption architecture with key scheduling employing the four s-box structure is implemented.The complete compact encryption-decryption system has a small size requiring about 7.5K gates and the throughput of the circuit is 132.92 Mbps.