Design And Implementation Of Cache Core Based On Secure SoC Chip

As one of the components of information system,security chip is widely used in finance,military,banking and other fields,which is closely related to our life.It is essential to ensure the security of data in the process of transmission.And with the rapid development of computer technology,the speed "Memory Wall" between the CPU and the main memory of the central processor is more and more serious,which seriously affects the performance of the microprocessor.Cache technology is a key technology used to solve the speed matching problem.In a secure So C chip,CPU's access to main memory requires efficient data reading by the Cache on the one hand,and security protection during data transmission on the other hand.The research and design of the Cache core is based on a secure So C chip.Starting from the secure chip structure,combining the Cache design principle and the secure data Cache Cache.The configurable cache core function,different reading strategies of ordinary data and secure data,the design of efficient data DMA handling and the safe data stealing in dual bus mode are realized.This paper first summarizes the development and research status of Cache technology,studies the principle of Cache technology in detail,deduces the main memory access efficiency formula,and defines the Cache optimization method according to the access efficiency formula.At the same time,it explains the IC design method and process used in the research.In this paper,according to the practical application,the Cache core capacity is designed to be 64 KB,data row size is selected to connect with the secure AES module interface 128 bits and the 4-way group connection mapping mechanism to complete the address mapping.The module division and sub-module design of the secure Cache core,data transmission process and the Cache core state machine design are completed.To increase the LRB facilitate rapid continuous order a data read read and reduce the power loss caused by continuous access to Ram Cache data combine Cache with Buffer.Add a data line fill buffer LFB is used to encrypt data block splicing,four LRU replace strategy respectively to write data stone buffer STB and dirty data eviction Buffer EB,solve the secure data reading and writing with main memory update Cache competition issues,which can effectively improve the efficiency of Cache data to read.In view of the low hit rate caused by Cache data scouring caused by data handling in DMA mode,a pass-through function is designed for data in DMA mode to prevent Cache data from being replaced.When two CPUs of secure So C chip access the Cache,because of encryption and decryption of secure data,one of the CPUs occupies a large number of Cache time cycles,during which the Cache does not interact with data and cannot read data for another host.In order to solve the problem of efficient data reading under two hosts,Cache data security theft is added.In addition,according to the data structure of the security Cache,the paper studies the security algorithm,the algorithm analysis of Cache-based high-speed AES decryption algorithm module and the CRC real-time verification module as well as the hardware optimization,and realizes the circuit design of the optimized security algorithm.This paper adopts the bottom-up design method and uses HDL to write the RTL function code of the secure Cache core.This paper implements simulation verification,testing for the security Cache designed and implemented at the module level and system level,focusing on the simulation verification of the data interaction between the security algorithm module and the Cache module,and the memory access efficiency test of the Cache when the security algorithm is turned on.Through targeted verification test cases,the main Cache behaviors such as Cache allocation,replacement,and stealing,as well as the correctness of the related access of the relevant main memory address are verified.The Cache is verified by system-level test to verify the accuracy of access under system simulation,so as to ensure the correctness of the design of the secure Cache core.The verification results show that the security Cache has reached the functional requirements of the design,and the test results demonstrate that the designed security Cache has reached the design goal.In addition,DC synthesis of the secure Cache core is carried out.After repeated verification and tests,the performance of the secure Cache core reaches the design requirements.