Design And Verification Of Real-time Monitoring System Based On ARC Processor

With the continuous development of integrated circuits and the advancement of Moore’s Law,the scale and complexity of chips are increasing,which poses more and more challenges to processor developers.How to improve the development efficiency of multi-core processors has become an urgent problem to be solved.The key to improving development efficiency is to improve the debugging ability of the processor.The traditional debugging method in the industry is VCS-based simulation verification,which makes it difficult to debug program exceptions and program deadlock problems.The debugging system based on instruction information can observe the actual execution process of instructions,so it can quickly locate program exceptions and program deadlock problems.The commonly used instruction debugging technology in China is the debugging scheme based on JTAG,which is intrusive monitoring and debugging,which brings great inconvenience to debugging.Therefore,designing a real-time monitoring system with non-intrusive access has become the focus of the development of the debugging system.Based on the research of real-time monitoring system at home and abroad,this thesis designs a set of real-time monitoring system of instruction information based on a dual-core processor of ARC.Its main function is to monitor the instruction information generated during the running of the processor program.Capture,control and store.The main adventages are strong configurability,various output interfaces,various types of commands that can be obtained,small resource occupation,and the ability to quickly locate target commands.The real-time monitoring system is mainly divided into filtering module,compression module,encapsulation module and Nexus arbiter module.The external output ports include Nexus interface and AXI interface.Developers can obtain instruction information from the Nexus interface and the AXI interface in turn through the MWDT debugging terminal to do further debugging work.In addition,in order to avoid the instruction overflow caused by the different input and output speeds of the internal buffer of the real-time monitoring system,the Freeze mechanism and the Wrap mechanism are designed.On the basis of the above work,by comparing the advantages and disadvantages of VCS simulation verification and FPGA prototype verification,in order to ensure the completeness of the verification work,two methods are used to carry out the verification work respectively.Based on the VCS simulation verification method,a verification platform is built,and the important registers,key modules,external output interfaces and key mechanisms of the realtime monitoring system are fully verified.Through the simulation waveform and code coverage analysis,it can be seen that the functions of the real-time monitoring system are normal.It meets the design expectations;then build a prototype verification platform based on HAPS-80.When the FPGA clock is 50 MHz,no timing violations or excessive resources are found on the XCVU440 chip.The real-time monitoring system functions on the FPGA as expected,and does not integrate real-time monitoring.Compared with the performance of the system’s ARC processor,the Dhrystone score fluctuates less than 0.1%,indicating that the design of the real-time monitoring system does not bring performance problems to the ARC processor.Finally,the maximum output bandwidth of the real-time monitoring system is studied,and four methods for improving the maximum output bandwidth of the real-time monitoring system are obtained,and the theoretical maximum output bandwidth is 450MBytes/s,thus completing all the design and verification of the real-time monitoring system.