Research On Multi-core Architecture And Prototype Implementation Technology Of Multi-Processor System-on-Chip And Network-on-chip

Multi-core technology has been applied in more and more products by famous companies in recent years. For example, Core 2 Duo from Intel and Athlon 64 FX from AMD both are dual-core chips. The Niagara processor from SUN has 8 cores and the CELL processor from STI (SONY, TOSHIBA and IBM) has 9. ARM's MPCORE integrates 4 ARM11 cores.Multi-core technology has been in the academic research even earlier. MPSoC (Multi-processor System on Chip) and NoC (Network on chip), which are the key multi-core technology, were proposed in around 2000. From then on, more and more research projects have been set up such as KTH's NOCARC, Stanford University's Netchip and Manchester University's Marble.The above facts indicate that MPSoC-NoC multi-core technology may replace the current SoC (System on chip) to be the main design technology in the next generation VLSI IC (integrated circuits) design. In the SoC era, the IC technology has become the cross subject among Semiconductor, Electronics, and Computing. As time going on, computing technology and the computer architecture may become the key point in the innovation of IC design. So the system engineers may take a more important role in the high end chip projects. The appearance of multi-core technology has begun and it has brought radical transformation in IC architecture and an unprecedented broad development space for high end IC design.The research objects in this article mainly focus on the MPSoC-NoC multi-core chip architecture, the design, development and implementation of several kinds of MPSoC-NoC prototype chips. The main contribution is as follows.1. Proposed 5 kinds of MPSoC-NoC system architecture which are from single bus based MPSoC, hierarchy bus based MPSoC, point-to-point I based NoC and point-to-point II based NoC to two-dimensional mesh NoC. Running mode and programming model were analyzed in each case. And the influence of the communication mechanism on the system performance was discussed. Finally an MPSoC-NoC formal model was proposed based on the BPM (Backbone, Platform and Mapping) classification method.2. Implemented 4 kinds of MPSoC-NoC prototypes excepting the point-to-point I based NoC. Each kind of basic prototype integrated 4 processors, and the frequency was up to 60 MHz. Targeting at simple actual application, 3 kinds of improved prototypes were implemented by adding VGA interface and other modules, which were 4-core hierarchy bus based MPSoC, 6-core point-to-point II based NoC and 8-core two-dimensional mesh NoC.3. Established the performance test environment based on the prototype chips. The performance evaluation and the parallel programming on methodology of MPSoC-NoC prototype were studied. Performance evaluations were done on the 4 basic prototype chips. The experiment results show that the two-dimensional mesh based NoC is superior to all the other architecture not only in speedup but also in extensibility.4. The definition and the basic theory system of MPSoC-NoC were preliminaryconcluded. And several assumptions such as the reconfigurable MPSoC-NoC and thedouble-cores-in-one-node NoC architecture were proposed.