Implementation And Research Of RISC-V DSP Microprocessor And SoC

Computer architecture has evolved over the past decades of computer development history.Therefore,many computer instruction set architectures have been created in the past few decades.Today,there are several mainstream instruction set architectures,such as x86,ARM,MIPS,and Open RISC.Entering the 21 st century,the concise and straightforward RISC instruction set has become the mainstream ISA of microprocessor design,while the existing RISC instruction sets such as MIPS,SPARC,and ARM have more or less defects leftover from the history.In order to solve this problem,Berkeley University launched the fifth-generation RISC project in 2010,designed a new RISC-V instruction set architecture,which is characterized by open-source and provides many technical features of modern microprocessor design,including optional extension instruction sets,custom instruction capabilities,and separation of user and privilege architectures.Based on the characteristics mentioned above,RISC-V microprocessors are rapidly occupying the market other than desktop microprocessors.At the same time,with the continuous improvement of the microprocessor architecture,the tools and frameworks for designing microprocessors also face the challenges of efficiency and productivity.Traditional integrated circuit design tools and methodologies,such as the waterfall design pattern based on Verilog/System Verilog,are becoming stretched.On the other hand,with the rise of design tools based on agile hardware design methodologies,such as Chisel and Spinal HDL,various novel hardware design tools and frameworks based on high-level programming languages and software engineering methods have gradually been accepted by academia and industry.This article design a RISC-V open-source DSP embedded microprocessor and So C.It implements the RV32 GCP instruction set,which can match the performance of the embedded microprocessor design by ARM: Cortex-M3.The microprocessor can enrich the implementations of the domestic open source RISC-V DSP microprocessors,and provide the industry with more choices of RISC-V DSP microprocessor IP cores.At the same time,this paper also proposes the hardware design and verification framework Py HCL used to build the microprocessor.PyHCL is the first RTL-level hardware construction language based on Python.Py HCL provides a more straightforward and easier-to-use user interface,short learning curve,and full Python feature support compared with Chisel.The efficiency of Py HCL is better than Chisel.Compared to Chisel,which only supports unit testing,Py HCL has complete verification environment support,including unit testing,functional testing,and differential testing.This paper consists of two main parts: one is the design of the DSP microprocessor based on RISC-V,and the other is the agile hardware development framework Py HCL.