VLSI Design Of HEVC Inter-frame Coding For Car Safety Applications

In recent years,with the rapid development of the internet,5G communication,as well as AI and autonomous driving technology,the requirements for video resolution and frame rate by operating systems have become increasingly high.Compared to the previous generation of encoding technology H.264/AVC,HEVC(High Efficiency Video Coding)can significantly improve coding efficiency and is becoming popular in the field of video coding required for autonomous driving.Inter-frame coding is the most computationally intensive,complex,and time-consuming part of the entire video coding process.Due to the limitations of real-time software encoding,using hardware for design can significantly improve coding efficiency.On the other hand,autonomous driving systems require high video format requirements based on real-time and accurate surrounding scenery for vehicle control.Therefore,this paper conducts VLSI design for inter-frame coding of4K@90 fps after studying it.Motion estimation is the core part of inter-frame coding,so this paper investigates and studies the algorithm of motion estimation and designs a parallel raster search algorithm based on the characteristics of car driving.This algorithm can greatly increase the search range while ensuring coding accuracy and can encode irregular motion information.Subsequently,we build the VLSI architecture according to the algorithm,carry out the logic design of the circuit,and optimize the structure of some key parts.The MV prediction module implements weighted temporal and spatial motion information and optimizes cache design to provide two motion vectors in spatial domain while reducing area.For the critical reference frame cache design,the pixel reuse of the reference frame is first studied,and then a new cache method is designed based on the reuse and reading requirements,which matches a small window buffer and SRAM.This method can meet the reference frame data two-dimensional reading requirements of the search algorithm of this design while saving a lot of area and power consumption.This paper designs a 32×32 PE array according to the video encoding requirements of 4K@90fps,and optimizes the operation units of the PE array,reducing the use of calculation logic while satisfying the processing performance.For the introduced transform module,butterfly operation is used,and a Hadamard transform circuit satisfying double size blocks is designed by analyzing its data flow.The circuit can achieve full pipeline operation,and the usage rate of the operation array during operation can reach 100%.For SRAM,this design has a Hamming code verification mechanism,which can automatically correct 1-bit errors in data transmission,ensuring data security to a certain extent.Finally,the design is simulated and verified,and the circuit’s functional correctness is verified through the UVM platform after integration.The logic synthesis is completed using DC tools under the TSMC 22 nm process with a frequency of 450 MHz.Finally,FPGA and software co-simulation are performed,and the results show a reduced loss of image quality.