Design And Optimization Of Adder Within Memristive Crossbar Array

In the traditional von Neumann architecture,calculation and storage are physically separated,and a large amount of data needs to be transmitted during the computing process,facing the bottleneck of calculation speed and energy efficiency,which is regarded as the"von Neumann bottleneck".Computing in-memory(CIM)is one of the most promising methods to solve this problem,which combines data storage and processing in the same physical unit.Memristor is a passive electronic component with a memory function,which has the characteristics of low power consumption,high density,non-volatility,and compatibility with CMOS manufacturing process.It is one of the most potential candidates to break the"von Neumann bottleneck".In the existing literature,a complete logic set can be realized based on memristors,and any Boolean logic can be realized by iteration.However,the basic logic gates based on memristors still require a large number of memristors and operation steps.Based on the design of memristor logic circuits,this thesis studies and discusses Complementary Resistive Switches(CRS)logic and Majority-Inverter Graph(MIG)logic.Optimize the memristor logic design by increasing the memristor reuse rate.First of all,this thesis proposes an improved reconfigurable logic based on the CRS structure.By constraining the range of the high voltage V_H,in the process of executing the logic operation,it is ensured that the resistance state of at least one memristor in the CRS structure does not change.Increased reusability of memristors when implementing complex logic functions.The HSPICE simulation results verify the feasibility of the improved reconfigurable logic.Secondly,on this basis,six kinds of logic gates are designed in this thesis,including AND,OR,Material Implication(IMP),Not-material Implication(NIMP),XOR and XNOR logic gate,where AND,OR,IMP,and NIMP logic gates can be implemented using two memristors and one operating step,XOR and XNOR logic gates can be implemented using three memristors and two steps to implement.According to different initial states of memristor,two methods to realize AND,OR and NIMP logic gates are designed.The HSPICE simulation results verify the feasibility of the method.In addition,the shielding problem of the memristors that are not in the same row as the selected memristors in the memristor crossbar array is also studied,and the performance of the crossbar array structure is improved.Then,based on the compatibility between the proposed improved reconfigurable logic and MIG logic,both the two logics are integrated into one crossbar array to design and optimize complex logic circuits.On this basis,this thesis designs a one-bit full adder,which uses five memristors and six operating steps to complete the calculation.Finally,this thesis also designs 2-1 multiplexers and 4-1 multiplexers based on the proposed improved reconfigurable logic.And proposes two methods for the 4-1multiplexer,namely a speed-first method and a data-protection-first reusable method,wherein the speed-first method may corrupt the stored value,which is related to the selected data and the selection signal.Compared with other methods,the logic gates,one-bit full adder,2-1multiplexer and 4-1 multiplexer which based on the proposed the improved reconfigurable logic in this thesis,have reduced the number of memristors and operation steps.