Research On The Test Methods Of Memristor Crossbar Arrays

With the rapid development of very large scale integrated(VLSI)technique,the number of transistors in an integrated circuit(IC)increases exponentially.However,under the limits of the microelectronics techniques,the physical property of materials and financing,more challenges are encountered to further reduce the feature size of the chips.Since 1970's,Leon Ong Chua,a Chinese-American scientist,predicted that there is a fundamental component,named memristor,except for resistor,capacitor,and inductor,which is provided a functional relation between charge and flux.In 2008,a team at HP labs,based on an analysis of a thin film of titanium dioxide,first connected the operation of resistive random access memory(RRAM)devices to the memristor concept.Memristors have the advantages of small feature size,low power consumption and high integration.The implementation of the memristors gives hope to extending to Moore's law,and significant technical renovation in consumer electronics.The memristors are used in memristive crossbar,which is formed by two sets of parallel nanowires crossing perpendicularly and devices at each crosspoint.According to the different devices at the crosspoint,the memristor crossbar mainly divided into one memritor(1R)and one transistor one memristor(1T1R)crossbar structure.Except that,there is CMOS/nanowire/Molecular(CMOL)structure,which is similar to 1R crossbar.The memristor crossbar has been mainly applied to RRAM,neural network and logical circuits,and has important application prospects.Due to the immature manufacture process of memristor,with the mass production of the correlation circuits of the memristive crossbar,the research on the reliability of memristive crossbar will be one of the key research issues in the near further.Now,the research on memristive crossbar testing is limited.There are only a few research groups have related work,and focus on the defect analysis and fault models.The performances of test algorithm still need to be improved,because the use of the structure information is not enough.The problem of drafting solving in this thesis is keeping the high fault coverage and reducing test time,so as to improving test efficiency.This thesis starts from the memristor model,through drawing lessons from the test method of traditional RAM,based on the characteristics of different structure of the crossbar,proposed the test methods for the different memristor crossbars.This thesis mainly includes the following contributions:(1)According to the faults modeled the defects in a memristor of 1R crossbar caused by parametric variation during its fabrication and the coupling fault models caused by the bridge defects between nanowires.This thesis proposes a logic operation-based design for testability(DFT)architecture for 1R crossbar testing.In this architecture,memristor-aided logic(MAGIC)NOR gates are embedded to check whether all the cells in the crossbar are Os or not at a time.A March-like test algorithm is also presented for the proposed DFT architecture,which covers all modeled faults.Compared with previous work,our method reduced one order of test time.For the further of reduced the test time,we perform the NAND logic in this structure to check whether the input memristors in the crossbar are Is or not at a time.By analyzing,when the numbers of the inputs in NAND logic are excessive,the differentiation degrees of the output voltage between without fault(all Is)and with fault(not all Is)are reduced,and then there is failure.Therefore,this method needs to consider the read and write precision of the circuit,set the proper number of the input in NAND logic,and then the test time is reduced drastically in the premise of keeping the testing effect.(2)This thesis proposes a March C--1T1R test algorithm for 1T1R crossbar.We analyse the pass-fail fault dictionary of the proposed test algorithm,which can detect all the modeled faults,including the fault models in traditional RAM(stuck-at,coupling and address decode faults),and fault models caused by the parametric variation of memristors(Deep-0,Deep-1,Slow write and Read 1 disturbance faults).Therefore,it is achieved complete fault coverage.The methods of the previous work cannot detect all the modeled faults.Since the fault coverage is most important for test algorithm,the proposed test algorithm in this thesis is more effective.(3)With keeping complete fault coverage,in order to further reduce test time,the logic operation-based DFT architecture and the parallel test algorithm is proposed in this thesis.This work is similar to the first part of the thesis,we added the memristors on a row for embedding MAGIC NOR and NAND gate.Therefore,the time of check whether all the cells in the crossbar are 0/1s or not is reduced.(4)According to CMOL circuit architecture,this thesis analyzes the electrical defects in a CMOL circuit including open and bridge defects,and the fault models of the CMOL circuit architecture are obtained.A parallel March-like test algorithm,named as March-CMOL test algorithm,is presented for the CMOL architecture for the first time,which covers all the modeled faults caused by the electrical defects.The March-CMOL test algorithm is word-oriented,and considered the characteristic of CMOL circuit architecture,proposed the idea of hierarchical structure test.In this method,using the base cells in CMOL circuit architecture detect the coupling faults in CMOS layer.The faults in the multicell can be detected in parallel.Therefore,the test time of the proposed test algorithm is reduced significantly.