Design And Optimization For Digital Circuit Within Memristive Crossbar Array

The emergency of transistors results in an epoch-making revolution in electronic technology,which is the basis of the development of modern electronic technology and the symbol of the development of microelectronic technology.However,with the growth of data in today's society,people have to find a new generation of memory devices due to the bottleneck of traditional von Neumann architecture and the problem of memory wall.Memristor is considered as the most potential candidate to replace transistors due to its characteristic of nonvolatile resistance transition,low power consumption,high speed and compatibility with CMOS process.In recent years,memristor has been proved to be used in nonvolatile logic operations,it implements the integration of storage and calculation in a real sense,which has attracted extensive attention of researchers.Based on the research of memtistive logic circuit,this thesis discusses memristive material implication(IMPLY)and not-material implication(IMPLY)logics,and studies the implementation of the negative bias N-IMPLY scheme.The positive bias N-IMPLY scheme is proposed and verified by the simulations with the defect ionic memristor(DIM)model and voltage threshold adaptive memristor(VTEAM)model to prove that N-IMPLY logic can be executed between the memristors on the same word or bit lines.Based on the similarity between the circuit structures of IMPLY and N-IMPLY logics,a novel method for the digital circuit design is proposed that both IMPLY and N-IMPLY logics are integrated into one crossbar array.Six basic logic gates are designed by utilizing iterative operations of two logics.In addition,this thesis provides two different implementations for gates XOR and XNOR,which aim for the optimizations of area overhead and the number of operation steps,respectively.The designed gates are simulated by using Virtuoso simulation software,verifying the feasibility of the proposed method.The phenomena of sneak path in the array is also studied and simulations are performed to expound that the sneak path will affect the correctness of the logic execution.To solve this problem,we apply isolation voltages to the unselected nanowires to isolate the memristor cells that the sneak path flows through,which alleviates the impact of sneak path on logic execution.The feasibility of this method is verified by simulation,which improve the performance of the cross array structure.To verify that the proposed method can be applied to the design of complex digital circuits,a 1-bit full adder and multiplexers are designed in this thesis.By reusing the initial data stored in the memristors and the intermediate operation results,the area overhead and the circuit delay are optimized.Compared with other approaches,the performances of the circuits are improved in our method.Moreover,the impact of parameter variation of memristors on circuit is also analyzed in this thesis,in which Monte Carlo method is used to simulate the impact of memristor on the calculation of circuit when the resistance,set voltage and reset voltage of the memristor fluctuate.Simulation results show that the designed citcuit exhibits a fantastic robustness and stability.