Research On The Circuit Simulation And Physical Device Implementation Of The Memristor Crosspoint Array

Faced with the urgent demand of large-scale data storage in the era of large data,the traditional large-capacity non-volatile storage technology is lack of stamina.It is ur-gent for Industry and academia to research and develop new large-capacity non-volatile storage technology in order to effectively alleviate the current and future challenges of large-scale data storage.As one of the most promising non-volatile storage technologies,memristor arrays have the advantages of long durability,non-volatility,high speed,high density and low power consumption.However,the process of its commercialization and commercialization is still facing the scientific and technological problems of circuits and devices.In this thesis,the application of memristor array in non-volatile storage is studied from circuit simulation and physical devices implementation.The main achievements are summarized as follows:In Chapter 2,aiming at the controversy about the worst read scenario of the memristor array in academic community,we use Gauss-Seidel iteration method to simulate the whole array of the readout operation of the memristor array.The worst read scenario of the memristor array is comprehensively analyzed from two aspects:selected locations and data patterns.At firt,with randomly distributed HRS and LRS in the memristor array,we define that the worst selected location is located at the furthest corner from the word-line and bit-line in the memristor array,by studying the impact of the selected location on the read current.Then,the influence of data pattern on the read current is studied and analyzed.When reading LRS,the read current is mainly affected by the shunting effect of the parasitic sneak paths,and the worst data pattern is that all unselected memristors in the array are in LRS.When reading HRS,the read current is mainly affected by the trade-off between the shunting effect of the parasitic sneak paths and the current injection effect of the parasitic sneak leakage.These two effects are related to the device and circuit parameters of the memristor array.Therefore,the worst data pattern needs to be discussed according to the situation.In dealing with that,we propose a concept of the threshold array size N_thincorporating the trade-off to define the parameter-dependent worst data pattern.This figure-of-merit provides guideline for the worst read scenario analysis of the memristor array.In Chapter 3,a flexible circuit-lumped model is proposed to improve the computa-tional efficiency in the simulation of large memristor arrays.The circuit-lumped model can reasonably simplify the memristor array by flexibly selecting reduction coefficients.Under the worst read/write case of the memristor array,we simulate and verify the circuit-lumped model from four aspects:array resistance,read operation,write operation and power consumption.The simulation results show that the circuit-lumped model of the memristor array can effectively improve the simulation efficiency and save the simulation memory cost while ensuring the simulation accuracy,thus providing technical support for the performance evaluation,design and application of the memristor array.In Chapter 4,we take the 1S1R memristor array as an example to investigate the design space of the selector from device and array level.The interdependence between different device and circuit parameters is simulated and analysed from the bottom-up com-prehensively,which can provide guidelines for the design and optimization of device and circuit in 1S1R memristor array.At first,we simulate and analyse the impact of the se-lector on the characteristics of the 1S1R full cell.Different properties of the 1S1R full cell have different dependence on the parameters of the selector.Therefore,to optimize the characteristics of the 1S1R full cell,it is necessary to weigh the effects of the selector on the properties of the 1S1R full cell.Then,we study the influence of different bias schemes on the design space of the selector for a 1 Mbit 1S1R memristor array under specific performance constraints.From the point of view of satisfying the tolerance of read/write operation,the bias schemes that can optimize the design space of the selector are V/3,Floating and V/2 according to the space size of order.From the point of view of satisfying the power consumption of read/write operation,the bias schemes that can op-timize the design space of the selector are Floating,V/2,V/3 and GndFloating according to the space size of order.Finally,taking the V/2 bias scheme as an example,we simulate and analyse the influence of the properties of the memristor on the design space of the selector in the 1 Mbit 1S1R memristor array.In Chapter 5,Au/Ti/TiO₂/Au memristor arrays are fabricated.The impact of the Forming process and the intrinsic structure of the device on the switching behaviour of the TiO₂film memristor and its underlying physical mechanism are studied through mate-rial characterization and electrical characterization.Under different Forming compliance,Au/Ti/TiO₂/Au memristors exhibit bipolar or step-wise resistive switching behaviour.By fitting and analysing the conduction mechanism of HRS and LRS,we qualitatively explain the resistive switching behaviour under two different Forming conditions by using the conductive filament model.In order to study the impact of the intrinsic device structure on the resistive switching behavior in Au/Ti/TiO₂/Au memristor,similar electrical charac-terizations are carried out for the non-Forming Au/Ti/TiO₂/Au memristor.It is found out that the non-Forming Au/Ti/TiO₂/Au memristor exhibits the intrinsic switching I-V char-acteristic,which can be reconstructed analytically by decomposing the Au/Ti/TiO₂/Au memristor into a 2R structure composed of the switching layer and non-switching layer.The experiment results can provide guidelines for the preparation and application of the memristor device.