Design And Development Of A High-performance Controller Of A RF Switch

With 146 years of history,from wired to wireless,wireless communication has been throuth the first generation to the fifth generation and the way of communication has changed dramatically.Nowadays,people can get their food,clothing shelter and transportation via a mobile phone.Under the influence of the coronavirus epidemic,trave card records one's trips and health Quick Response code update personal infection status in real time.Both of them are inseparable from base stations and mobile phones.The RF front-end circuit is the key for base stations and mobile phones to send and receive information.RF switch plays a key role in frequency band selection,path selection of multi-antenna technology,and multi-function selection of mobile phones and other portable electronic devices.The RF switch controller is the control module of the RF switch,which provides the appropriate DC bias voltage to the RF switch power device according to the given control signal to control the working mode of the RF switch.A good performance RF switch controller can maintain low power consumption while providing a stable bias for the RF switch with a fast setup and switching time.Therefore,the research and design of a high-performance RF switch controller is of great importance.This paper first introduces the common architecture of rf switch and its DC bias mode,and then introduces the functions and structure of the controller.Compared with the bulk silicon CMOS process,the advantages of SOI CMOS technology in RF switch and its controller design are described.Secondly,based on 0.18?m SOI CMOS technology,a DPDT switch controller is designed,which integrates bandgap voltage reference circuit,linear voltage regulator,negative voltage generator,three-value logic drive circuit and so on.The power supply voltage of the design is 2.8V,the voltage is established within 6.12?s,the bias conversion is realized within4?s,and the DC power consumption is 44.4?A during steady-state operation.The area of the chip layout is 0.75×0.35 mm2.The chip was tested and the negative pressure establishment time is 6.5?s,and the static power consumption is 55.9?A.Finally,based on the 0.18?m SOI CMOS process,this thesis also designed a SPDT controller,for its power supply voltage is as low as 1.8V,a new frequency hopping voltage doubling circuit is proposed to achieve faster establishment and conversion speed and lower power consumption.The traditional charge pump circuit uses a constant frequency clock to supply the charge pump.The fast establishment and recovery time requires a high clock frequency,and a high clock frequency will bring a large current,resulting in a high power loss.The proposed circuit has a high clock frequency during establishment and switching time to speed up establishment or output recovery.After short period of time the clock frequency will decrease to reduce power consumption.The establishment time of positive output of the SPDT switch controller is 3.795?s,and the recovery time of control signal conversion is 1.396?s.The establishment time of negative output is 5.293?s,the recovery time of control signal conversion is 2.257?s,and the dc power consumption is 16.81?A when the switch is working at steady-state status.The design saves 28.6% power consumption compared with conventional voltage doubling circuit while maintaining nearly the same conversion rate,and the current power consumption is reduced by 36.7% after the switch enters steady state operation.