Design And Development Of Quasi Real Time Acquisition System For Time Domain Radar

Time domain radar is an important means of detection,which has characteristics of wide spectrum,low power spectral density and high peak power,so compared to the ordinary frequency domain radar,time domain radar's detection resolution and distance has a natural advantage.In the reception of radar signals,high-speed analog radar signal needs to be convert to low-speed digital signals,so the study of its acquisition system is important to the development of time domain radar.Starting from the development of time domain radar receivers,the thesis analyzes various signals used in time domain radar systems commonly,considers several sampling methods comprehensively and gives a detailed analysis process,discusses different sample-and-hold structures and operation amplification circuits,calculates the parameters of the core components of the sampling pulse circuit,and studies how to generate delay of signal.The thesis uses a four-tube balanced gate circuit as sampling gate circuit,due to the symmetrical design,the sampling pulse needs to be a pair of signals with the same amplitude of the opposite polarity.The integral amplifier is mainly used for waveform conversion or integral compensation,so the selection of proportional operation amplification circuit is used to amplify the sampled signal.The hold-circuit is based on the RC circuit and used to widen the sampled signal.When generating a sampling pulse,due to the fact that the Marx circuit can output a very narrow pulse signal,a 6-stage Marx circuit and a sharpening capacitor are added,so the half-peak width of the sampling pulse can reach 300 ps,and the unipolar signal is changed into a symmetrical bipolar signal with a balun circuit.In the design of sampling method,the real-time sampling and equivalent sampling were compared,dynamic near-real-time sampling method was selected,in order to prevent the clock signal from changing and causing timing disorder,the method of delaying the phase of the sampling pulse is selected,and the counter inside FPGA and the IODELAY module were used to achieve an accuracy of 100 ps and a delay ranging from 0-10.5 ms for the sampled pulse signal,the sampling rate can reach 10 Gsps.After the design is completed,the various modules are combined to test,and the unipolar Gaussian pulse is received and tested,the original signal can be restored accurately.