Design And Implementation Of PCIe?DMA In SSD Controller

With the development of the global economy,information technology has been widely used.With the rise of industries such as cloud computing,virtual servers,and AI,the performance requirements for storage are getting higher and higher.Traditional mechanical hard drive can no longer meet these high-performance requirements.Solid State Drive has been widely used in many fields due to its small size,low power consumption,low noise,fast speed,and good shock resistance.Therefore,it is very important to analyze its structure and improve performance.The key components of the SSD are the controller and storage media.The high-performance SSD has an independent ARM core inside to implement the FTL algorithm.Starting from the structure of the SSD,to improve the performance can be considered from the following aspects: selecting a better performance storage medium,optimizing the design of the controller,and adopting a software interface standard with a higher link speed.Nowadays,the performance bottleneck of the memory has risen from the bottom storage medium part to the top controller performance part.Therefore,this article starts from the perspective of optimizing the controller to improve the performance of the SSD.In this design,PCIe is used as the interface between the host and the SSD,and the Nand flash memory is used as the main storage unit.At the same time,it follows the NVMe software protocol.On the basis of the PCIe interface SSD controller,in order to improve the efficiency of Host's access to the solid state drive,by adding 128 threads responsible for polling and detecting the CPU,the command configured by each thread is taken in a polling manner,and each thread can be used.The thread polling module configured with16 Flash channel commands and the out-of-order processing module responsible for sorting the messages returned by the Host,as well as the access command field definition negotiated by the software and hardware,realize the parallel access to the multi-channel Flash by the multi-thread on the Host side Function.The 128 threads of the host CPU can access 16 Flash storage channels,and there is no binding relationship between threads and channels,so that the CPU side can balance the load and extend the life of the entire solid state drive.Cooperating with the host side to disperse and process flash memory access commands,multiple Flash channels can work in parallel,reducing the time required for read and write access.The PCIe?DMA transmission engine in the design has no coupling relationship with the receiving engine,which can give full play to the full duplex performance of the PCIe link and improve bandwidth utilization.At the same time,the DDR4 SDRAM cache is mapped to the PCIe BAR2 space to support passively receiving and responding to data transfer requests sent by the external DMA engine,which can be applied to the end-to-end access of other PCIe devices to the SSD.On the basis of the above-mentioned improvement scheme of SSD controller performance,this article has determined to implement the controller logic on the Altera arria10 series FPGA board.First,use the synthesizable Verilog language to implement the design of each sub-module in PCIe?DMA,then extract the functional points that the design module needs to verify and formulate a verification strategy,and then use the System Verilog language to build a verification platform based on UVM,and the method of generating incentives is explained in detail.Then the PCIe?DMA module and the entire SSD controller subsystem are verified for function.By viewing the simulation report and waveform analysis,it is found that the design can achieve the logic function well;finally,the FPGA board verification shows that the design function is correct.After several tests,the rate of Host accessing the SSD can be roughly calculated.It can be seen that multi-threading improves the parallelism of the Flash channel work and reduces the access delay.It can be seen that the PCIe?DMA module designed in this article has played an important role in improving the performance of the entire SSD.