Design Of The PCIe Protocol Adaptation Layers Based On MicroBlaze

In the computer and industrial systems, high-speed data exchange within devicesis often occurred. With the increasing of a data transmission rate, the issue is thattransmitting data as some protocol causes the asynchronization, which results in theloss of data. The situation is even more serious when the transmission rate is up toGbps. The key to solve this problem is to add a protocol adaptation layer which canbe implemented in hardware.The WiGig Alliance defines Protocol Adaptation Layers (PAL) that supportspecific data and display standards over60GHz. The initial PAL are audio-visual(A/V), which defines support for HDMI and DisplayPort, and input-output (I/O),which defines support for USB and PCIe. PAL enables highly efficientimplementations because they are defined directly on the WiGig MAC and PHY,rather than layered on other protocols and can be implemented in hardware. Thismaximizes performance and reduces power consumption.The WiGig Definitions of PAL exist for USB3.0and PCIe. However, there areno Xilinx development boards for USB3.0. Therefore, this paper focuses on PCIe.The PCIe PAL hardware platform is created based on the Xilinx Virtex-6FPGA. First,the PC driver feeds the data into FPGA via PCIe. Then, the received data are flowedinto AXI4and processed by MicroBlaze soft-processor. After that, the processed dataare transmitted to the next level FPGA via GTX high-speed transceiver. Afterverification and optimization of the entire system using CSP formal language, thePAL platform is tested on the Xilinx ML605development board. The data rate fromPC to FPGA is up to6.4Gbps and the data rate between two FPGAs is up to3.2Gbps.