System level ESD failure mechanisms, analysis and test method

This dissertation, composed of four papers, discusses three topics related to system level electrostatic discharge. In the first paper, the discharge current and the transient fields of an ESD generator in the contact mode are numerically simulated using the FDTD method. The simulated data are used to study the effect of design choices on the current and fields. They are compared to measured field and current data using multi-decade broadband field and current sensors. The model allows accurate prediction of the fields and currents of ESD generators, thus it can be used to evaluate different design choices.; The second and the third papers derived a reference ESD event for human-metal ESD from measured discharges. It is characterized by current, current derivative fields and induced voltages. Further, it is shown that the peak-to-peak value of the voltage induced in a small loop correlates with the failure level in fast CMOS devices. The peak-to-peak voltages and the spectral content of the induced voltages vary greatly between different brand ESD generators. The data supports that a revised ESD standard will reduce the test result uncertainty if current derivative and most of all, the induced voltage are included as specifications for the design of ESD generators.; In the fourth paper, a three dimensional ESD scanning system which has been developed to record the ESD susceptibility map for printed circuit board is presented and the mechanisms that the ESD event couples into the digital devices is studied. The ESD susceptibility of a fast CMOS EUT is characterized by generating the susceptibility map of the EUT. A series of measurements of the noise coupled into a sensitive trace and pin during an ESD soft error event are presented.