Design And Implementation Of Data Recorder Based On Aurora Protocol

With the rapid development of high-speed integrated circuit and communication technology,imaging equipment with high frame rate and high resolution is widely used in aerospace and national defense fields.The resulting high-speed mass data brings severe challenges to the collection and storage of recording equipment.In order to meet the needs of high speed data acquisition in related fields,this design is committed to realizing a data recording device that can meet the needs of high speed data transmission and reliable storage.Firstly,in order to receive two 10 Gbps optical fiber signals,Aurora transmission protocol is adopted,and the Aurora interface circuit is designed through the cooperation of photoelectric conversion module and high-speed serial transceiver.The Aurora IP core is used to implement high-speed serial transmission of data streams,and disconnection reconnection and retransmission mechanisms are added at the protocol layer to improve the reliability of transmission links.Secondly,LVDS image interface circuit is designed to receive two 480 Mbps image signals.Aiming at the problem of frame loss and bit error caused by wrong link construction in LVDS transmission,the link construction mechanism was analyzed,and the link was optimized from two aspects of electrical isolation and receiving logic.Meanwhile,training frame was introduced to avoid invalid receiving state in link construction.Finally,in order to achieve reliable storage of multi-channel high-speed data,the multi-channel data stream is first programmed and packaged,then the data interaction between high-speed transmission and low-speed storage is solved through DDR3 logic control unit,and the Aurora IP core is used to achieve flexible and reliable high-speed serial communication between acquisition device and storage device.The storage rate and capacity of the recording device can reach 560MB/s and 256 GB respectively through the dual-plane and multi-LUN pipeline storage mode of 16 NAND FLASH chips.A retransmission feedback mechanism based on CRC check code and packet count is designed to improve the correctness of data read back.The correctness and function of the data recorder design were tested comprehensively by building a test platform.The test results show that the equipment can stably fulfill the requirements of various tasks and the function and performance indicators meet the requirements of the task.