Design Of 12.5GHz PLL And LDO Integrated Circuit Used In Optical Receiver

As the volume of information continues to grow and the world tends to be interconnected,there is a need for communication systems with greater capacity and faster transmission speeds.Optical fiber communication has obvious advantages and is widely used,and it is a key technology for high-speed information transmission.The main research content of this dissertation is the design of phase-locked loop(PLL)used in clock data recovery circuits and the low dropout linear regulator(LDO)circuit used in optical receiver front-end amplifiers.PLL and LDO are both important functional modules in the optical communication system,which affect the overall performance of the communication system,so it is of great significance to study them.In this dissertation,the key module circuit design,loop optimization and layout design of the phase-locked loop are completed in 40 nm CMOS process.In order to take into account the stability of the loop and the lock time,a design method of loop parameters is described in detail.For the design of phase frequency detector,the "dead zone" elimination technology is used to improve the accuracy of phase discriminator.And an improved charge pump structure is selected,which uses bootstrap technology to effectively reduce the non-ideal effects of the charge pump.Then the frequency divider is realized by the CML high-speed prescaler cascaded with a five-frequency divider which is composed of TSPC D flip-flops.The layout size of the PLL circuit is 612?m × 515?m.The post-simulation results under typical conditions show that the output clock frequency of the PLL is 12.5GHz,the lock time is 3.4?s,the power consumption is 80.3m W,and the jitter is 2.57 ps.In this dissertation,the overall circuit of the LDO is designed in IHP 0.13?m Bi CMOS process.In the LDO,a PMOS that can provide a lower dropout voltage is used as a power stage,and a folded cascode structure is selected to implement an error amplifier.The layout size of the LDO circuit is 125?m × 94?m.The post-simulation results under typical conditions show that the output current range of the circuit is from 0m A to 20 m A.When the input voltage changes from 2V to 3.3V,the output voltage is 1.8V,the quiescent current is 73.4?A,the linear regulation rate is 0.47%,the load regulation rate is 1.51%,and the power supply rejection ratio at 1k Hz is-74.9dB.