Timing Analysis And Application Under Low Voltage

The low voltage circuit has gained an extensive attention due to the advantages of low power consumption,which are widely used in Io T and smart devices.As the voltage decreases,delay variation becomes more and more great and is no longer ignorable,which results in that the traditional timing analysis method is no longer applicable and brings new challenge in timing analysis.For example,due to the nonlinearity of the delay and process parameters,the delay distribution no longer follows the Gaussian distribution;due to the many types of gates,the correlation between stages varies greatly and is difficult to characterize;due to the nonlinearity of the delay and PVT,it needs to execute the timing analysis under multi-PVTs and takes several months to build the variation timing libraries.In view of the above problems,this dissertation proposed a decoupled semi-analytical statistical delay model.Firstly,a full-analytical statistical delay model of the inverter chain is proposed.The variance of the path delay is derived by output waveform and coupling capacitance equivalence,and the probability density function and quantization point data are obtained according to the property of the lognormal distribution.The statistical delay model of the inverter chain established in this way is not only a full-analytical model that can quickly calculate the statistical delay value,but also the delay variance of each stage is the sum of the function of the threshold voltage variance of the current stage and the previous stage.This makes the correlation problem between adjacent stages into an independent problem of the transistors' threshold voltage variation,which provides a new idea and direction for the subsequent correlation analysis in the complex combination path.Secondly,a decoupled semi-analytical statistical delay model of the complex combination path in a single PVT scenario is proposed.On the basis of the inverter chains model,the semi-analytical model extends the input slew from only input slew to fast and slow two kinds of slews,and extends the type of gate from only inverter to complex combination gates.By dividing the gate delay variation into delay variation caused by the threshold voltage variation of this stage and that by input slew variation,the delay variances of the gate and the path can be finally expressed as the sum of the step delay variance and the threshold voltage variation.Therefore,the model not only decouples the correlation between adjacent stages,but also reduces the characteristic time overhead at different input slews.Thirdly,based on the relative variability analysis,the decoupled semi-analytical statistical delay model in single PVT is expanded to multi-PVT scenarios.By studying the step delay variability at low voltage,it is found that it has no relationship with the load capacitance,which not only reduces the impact of different loads that further reduces the characterization time but also eliminates coupling capacitance equivalent problem.Then by studying the step delay relative variability at low voltage,it is found that it has no relationship with PVT,which further reduces the characteristic time overhead under different PVT scenarios again.So,the model is extended from a single PVT to multi-PVT scenario with few the characterization overhead.Finally,the proposed decoupled semi-analytical statistical delay model is verified on the ISCAS99 benchmark under TSMC28 nm technology.The comparisons with two analytical methods(“fix ?” and“no ?”)and LVF are made.For the statistical delay model under a single PVT scenario,the errors of the three characterization quantities(variance,sensitivity,maximum delay)are 4.56%,2.27%,and3.74%.Compared with the “fix ?” and “no ?”,they increase by 3.21 and 10.11 times,3.84 and 11.9times,1.76 and 2.89 times respectively.According to the results of the statistical model under a single PVT,the key metric is the calculation accuracy of the variance,so only the path variance errors are given under different PVT.For the statistical delay model under multi-PVT scenarios,compared with the “fix ?” and “no ?”,it improves 2.52 and 8.38 times,2.89 and 9.07 times,2.92 and 7.66 times under different process,voltage,and temperature.Compared with LVF,it is nearly the same in the accuracy,which are 4.5% and 4.0%,but its characterization time and the storage capacity of the variation library data are reduced by three orders of magnitude.