Modeling Of Cell Delay Distribution For Multi Process Corners

As the process advances,the feature size is gradually decreasing.On the one hand,the impact of process parameter fluctuation on delay under advanced process technology can no longer be ignored.On the other hand,the introduction of new physical effects has led to an exponential increase in the number of process corners that the chip needs to be verified.Therefore,this paper mainly studies how to quickly and accurately establish a cell delay distribution model for multiple process corners under the advanced process technology.Based on the Fast PVT numerical modeling method,a Nonparametric Density and Regression(NDR)algorithm is proposed for the influence of local process deviation on cell delay.A cell delay distribution regression model for multi process corners is established.The model is mainly divided into two parts: density estimation and regression estimation.The density estimation is based on the Monte Carlo simulation data of the cell to estimate the process parameter distribution and delay distribution respectively;the regression estimation is to establish the mapping relationship between the process parameter distribution and the delay distribution.In the density estimation stage,the NDR algorithm proposes a local optimal truncation point instead of the global optimal truncation point based on the nonparametric orthogonal series density estimation method,which improves the accuracy and speed of the density estimation.In the regression estimation stage,the NDR algorithm is based on the Gaussian regression model.And an optimal parameter selection strategy combining leave-one-out cross-validation method and genetic algorithm is proposed.As a result,the optimal kernel function bandwidth is obtained,and the accuracy and speed of delay prediction are improved.Moreover,regular terms are introduced to further enhance the generalization of the kernel regression model.In this paper,the SMIC 28 nm process CMOS inverter,two-input NAND gate,two-input NOR gate,three-input NAND gate and three-input NOR gate are taken as examples to verify the model proposed in this paper.The results show that the accuracy of-3 sigma yield and +3 sigma yield estimated from NDR are 91% and 52% higher than the log skew normal(LSN),respectively.In addition,the average convergence speed of NDR is 3 to 4 times faster than LSN and 5 to 9 times faster than the Monte Carlo method.